5962-9750701HXC datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> 5962-9750701HXC

Preview

5962-9750701HXC: DescriptionQuad-SHARC DSP Multiprocessor Family; CategoryThe embedded processor and controller Microcontrollers and processors; File Size708KB，48 Pages; ManufacturerADI; Websitehttps://www.analog.com

Download Datasheet Compare View All

5962-9750701HXC Overview

Quad-SHARC DSP Multiprocessor Family

Preview

Download Datasheet

View All

Quad-SHARC

DSP Multiprocessor Family

AD14060/AD14060L

PERFORMANCE FEATURES

ADSP-21060 core processor ( × 4)

480 MFLOPS peak, 320 MFLOPS sustained

25 ns instruction rate, single-cycle

instruction execution—each of four processors

16 Mbit shared SRAM (internal to SHARCs)

4 gigawords addressable off-module memory

Twelve 40 Mbyte/s link ports (3 per SHARC)

Four 40 Mbit/s independent serial ports

(one from each SHARC)

One 40 Mbit/s common serial port

5 V and 3.3 V operation

32-bit single precision and 40-bit extended

precision IEEE floating point data formats, or

32-bit fixed point data format

IEEE JTAG Standard 1149.1 test access port and

on-chip emulation

FUNCTIONAL BLOCK DIAGRAM

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2–0

FLAG

2, 0

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2–0

FLAG

2, 0

SPORT 0

TCK, TMS, TRST

FLAG

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

(ID

2–0

= 1)

SHARC BUS (

ADDR31–0

DATA47–0

MS3-0

RD, WR, PAGE, ADRCLK,

SW, ACK, SBTS, HBR, HBG, REDY, BR

, RPBA, DMAR , DMAG )

6–1

1.2

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

SPORT 0

TCK,TMS, TRST

FLAG

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

EBOOT,

LBOOT, BMS

EMU

CLKIN

RESET

SHARC_A

SHARC_B

(ID

2–0

= 2)

PACKAGING FEATURES

308-lead ceramic quad flatpack (CQFP)

2.05" (52 mm) body size

Cavity up or down, configurable

Low profile, 0.160" height

Hermetic

25 Mil (0.65 mm) lead pitch

29 grams (typical)

= 0.36°C/W

SHARC_D

SHARC_C

(ID

2–0

= 3)

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2–0

FLAG

2, 0

AD14060/AD14060L

Figure 1.

TIMEXP

LINK 1

LINK 3

LINK 4

IRQ

2–0

FLAG

2, 0

CPA

(ID

2–0

= 4)

SPORT 1

TDO

LINK 0

LINK 2

LINK 5

TDI

LINK 0

LINK 2

LINK 5

TDO

GENERAL DESCRIPTION

The AD14060/AD14060L Quad-SHARC is the first in a family

of high performance DSP multiprocessor modules. The core of

the multiprocessor is the ADSP-21060 DSP microcomputer. The

AD14060/AD14060L has the highest performance-to-density

and lowest cost-to-performance ratios of any in its class. It is

ideal for applications requiring higher levels of performance

and/or functionality per unit area.

The AD14060/AD14060L takes advantage of the built-in

multiprocessing features of the ADSP-21060 to achieve

480 peak MFLOPS with a single chip type in a single package.

The on-chip SRAM of the DSPs provides 16 Mbits of on-

module shared SRAM. The complete shared bus (48 data,

32 address) is also brought off-module for interfacing with

expansion memory or other peripherals.

The ADSP-21060 link ports are interconnected to provide direct

communication among the four SHARCs, as well as high speed

off-module access. Internally, each SHARC has a direct link port

connection. Externally, each SHARC has a total of 120 Mbytes/s

link port bandwidth.

Multiprocessor performance is enhanced with embedded power

and ground planes, matched impedance interconnect, and

optimized signal routing lengths and separation. The fully

tested and ready-to-insert multiprocessor also significantly

reduces board space.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

SPORT 0

TCK,TMS, TRST

FLAG

TDI

CPA

SPORT 1

00667-001

SPORT 0

TCK, TMS, TRST

FLAG

TDO

CPA

SPORT 1

TDI

LINK 0

LINK 2

LINK 5

TDO

LINK 0

LINK 2

LINK 5

TDI

CPA

SPORT 1

AD14060/AD14060L

TABLE OF CONTENTS

Specifications..................................................................................... 3

Electrical Characteristics (3.3 V, 5 V Supply)............................ 3

Explanation of Test Levels........................................................... 4

Timing Specifications....................................................................... 5

Memory Read—Bus Master........................................................ 8

Memory Write—Bus Master ....................................................... 9

Synchronous Read/Write—Bus Master................................... 10

Synchronous Read/Write—Bus Slave ...................................... 12

Multiprocessor Bus Request and Host Bus Request .............. 13

Asynchronous Read/Write—Host to AD14060/AD14060L. 15

Three-State Timing—Bus Master, Bus Slave, HBR, SBTS ..... 17

DMA Handshake........................................................................ 18

Absolute Maximum Ratings.......................................................... 27

ESD Caution................................................................................ 27

Pin Configuration and Function Descriptions........................... 28

Pin Function Descriptions ........................................................ 30

Detailed Description ...................................................................... 34

Architectural Features................................................................ 34

Shared Memory Multiprocessing ............................................. 34

Off-Module Memory and Peripherals Interface .................... 36

Link Port I/O............................................................................... 38

Serial Ports .................................................................................. 38

Program Booting ........................................................................ 38

Host Processor Interface ........................................................... 39

Direct Memory Access (DMA) Controller ............................. 39

Applications..................................................................................... 40

Development Tools .................................................................... 40

Quad-SHARC Development Board......................................... 40

Other Package Details................................................................ 40

Target Board Connector for Emulator Probe......................... 40

Output Drive Currents .............................................................. 42

Power Dissipation ...................................................................... 42

Test Conditions........................................................................... 43

Assembly Recommendations.................................................... 45

PCB Layout Guidelines.............................................................. 46

Mechanical Characteristics ....................................................... 47

Additional Information ............................................................. 47

Outline Dimensions ....................................................................... 48

Ordering Guide .......................................................................... 48

REVISION HISTORY

12/04—Rev. A to Rev. B

Format Updated..................................................................Universal

Changes to Specifications Section.................................................. 3

Changes to Development Tools Section ...................................... 40

Changes to Target Board for Emulator Probe Section .............. 40

Changes to Figure 27...................................................................... 42

Updated Outline Dimensions ....................................................... 48

Changes to Ordering Guide .......................................................... 48

10/97—Rev. 0 to Rev. A

4/97—Revision 0: Initial Version

Rev. B | Page 2 of 48

5962-9750701HXC Related Products

	5962-9750701HXC	5962-9750601HXC	AD14060	AD14060L
Description	Quad-SHARC DSP Multiprocessor Family	Quad-SHARC DSP Multiprocessor Family	Quad-SHARC DSP Multiprocessor Family	Quad-SHARC DSP Multiprocessor Family

Recommended Resources

Various secondary circuit diagrams and their explanations

Current reduction protection voltage stabilizing circuit

Speed control system with current negative feedback

BA2101 touch step dimming light circuit

025 Power supply circuit diagram of CASPER TM-5159 VGA color display

Positive ramp oscillator

TI Simplelink platform next generation wireless product solutions Q&A: 1. Can BLE and WiFi be compatible at the same time? How to deal with the compatibility between the two?TI provides a mechanism for the coexistence of WiFi and BLE, which can be learned from the latest...; fish001 Wireless Connectivity

MOS tube: Can MOS tubes be used as static switches?...; 无馨毓 Analog electronics

What are the methods to generate 4 square wave signals with different frequencies?: The question is this: I want to generate 4 square wave signals with different frequencies. The frequency of the signal is controlled at tens of kHz, but the frequency accuracy is very high. For exampl...; 燕园技术宅 Analog electronics

Flash usage issues: I want to use flash to store some useful data, but the information segment of flash is only 256B in size. It is too small, and I don't know which part of the main information segment is for programs a...; lvyiyong Microcontroller MCU

A very strange question?: [size=6][color=red]I want to know: Under what circumstances can a capacitor have the function of isolating direct current? [/color][/size]...; 黑山老妖88 Automotive Electronics

I'm looking for a multifunctional password lock based on LCD display: Can anyone provide a graduation thesis on a multifunctional password lock based on LCD display? I hope it can have a schematic diagram and program in C language or assembly language. Thank you very mu...; 249857121 MCU

Shortcut: S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 SA SB SC SD SE SF SG SH SI SJ SK SL SM SN SO SP SQ SR SS ST SU SV SW SX SY SZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 TA TB TC TD TE TF TG TH TI TJ TK TL TM TN TO TP TQ TR TS TT TU TV TW TX TY TZ U0 U1 U2 U3 U4 U6 U7 U8 UA UB UC UD UE UF UG UH UI UJ UK UL UM UN UP UQ UR US UT UU UV UW UX UZ V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 VA VB VC VD VE VF VG VH VI VJ VK VL VM VN VO VP VQ VR VS VT VU VV VW VX VY VZ W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 WA WB WC WD WE WF WG WH WI WJ WK WL WM WN WO WP WR WS WT WU WV WW WY X0 X1 X2 X3 X4 X5 X7 X8 X9 XA XB XC XD XE XF XG XH XK XL XM XN XO XP XQ XR XS XT XU XV XW XX XY XZ Y0 Y1 Y2 Y4 Y5 Y6 Y9 YA YB YC YD YE YF YG YH YK YL YM YN YP YQ YR YS YT YX Z0 Z1 Z2 Z3 Z4 Z5 Z6 Z8 ZA ZB ZC ZD ZE ZF ZG ZH ZJ ZL ZM ZN ZP ZR ZS ZT ZU ZV ZW ZX ZY

Popular Components