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CD74HC109EE4

Description
High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
Categorylogic    logic   
File Size461KB,16 Pages
ManufacturerTexas Instruments
Websitehttp://www.ti.com.cn/
Environmental Compliance
Stay tuned Parametric

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CD74HC109EE4 Overview

High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125

CD74HC109EE4 Parametric

Parameter NameAttribute value
Brand NameTexas Instruments
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerTexas Instruments
Parts packaging codeDIP
package instructionDIP-16
Contacts16
Reach Compliance Codecompliant
seriesHCT
JESD-30 codeR-PDIP-T16
JESD-609 codee4
length19.305 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeJ-KBAR FLIP-FLOP
Maximum Frequency@Nom-Sup20000000 Hz
MaximumI(ol)0.004 A
Number of digits2
Number of functions2
Number of terminals16
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
method of packingTUBE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2/6 V
propagation delay (tpd)60 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal surfaceNickel/Palladium/Gold (Ni/Pd/Au)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width7.62 mm
minfmax18 MHz
Base Number Matches1
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