74273 datasheet, PDF - EEWORLD Datasheet

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74273: DescriptionHC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20; Categorysemiconductor logic; File Size116KB，7 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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74273 Overview

HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20

74273 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	20
Maximum operating temperature	125 Cel
Minimum operating temperature	-55 Cel
Maximum supply/operating voltage	6 V
Minimum supply/operating voltage	2 V
Rated supply voltage	3 V
Processing package description	PLASTIC, DIP-20
state	ACTIVE
Craftsmanship	CMOS
packaging shape	RECTANGULAR
Package Size	IN-LINE
Terminal form	THROUGH-HOLE
Terminal spacing	2.54 mm
terminal coating	TIN LEAD
Terminal location	DUAL
Packaging Materials	PLASTIC/EPOXY
Temperature level	MILITARY
series	HC/UH
Logic IC type	D FLIP-FLOP
Number of digits	8
Output polarity	TRUE
propagation delay TPD	220 ns
Trigger type	POSITIVE EDGE
Max-Min frequency	24 MHz

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Octal D Flip-Flop with

Common Clock and Reset

High–Performance Silicon–Gate CMOS

The MC54/74HC273A is identical in pinout to the LS273. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of eight D flip–flops with common Clock and Reset

inputs. Each flip–flop is loaded with a low–to–high transition of the Clock

input. Reset is asynchronous and active low.

•

Output Drive Capability: 10 LSTTL Loads

Outputs Directly Interface to CMOS, NMOS and TTL

Operating Voltage Range: 2.0 to 6.0 V

Low Input Current: 1.0

µA

High Noise Immunity Characteristic of CMOS Devices

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

•

Chip Complexity: 264 FETs or 66 Equivalent Gates

MC54/74HC273A

J SUFFIX

CERAMIC PACKAGE

CASE 732–03

N SUFFIX

PLASTIC PACKAGE

CASE 738–03

DW SUFFIX

SOIC PACKAGE

CASE 751D–04

DT SUFFIX

TSSOP PACKAGE

CASE 948E–02

ORDERING INFORMATION

LOGIC DIAGRAM

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXADW

MC74HCXXXADT

NONINVERTING

OUTPUTS

Ceramic

Plastic

SOIC

TSSOP

DATA

INPUTS

CLOCK

PIN ASSIGNMENT

RESET

VCC

CLOCK

RESET

PIN 20 = VCC

PIN 10 = GND

GND

10/95

Motorola, Inc. 1995

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Design Criteria

Value

Units

Internal Gate Count*

Internal Gate Propagation Delay

Internal Gate Power Dissipation

Speed Power Product

1.5

5.0

µW

.0075

* Equivalent to a two–input NAND gate.

3–1

REV 6

FUNCTION TABLE

Inputs

Reset

Clock

Output

No Change

74273 Related Products

	74273	MC74HC273
Description	HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20	HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
Number of functions	1	1
Number of terminals	20	20
Maximum operating temperature	125 Cel	125 Cel
Minimum operating temperature	-55 Cel	-55 Cel
Maximum supply/operating voltage	6 V	6 V
Minimum supply/operating voltage	2 V	2 V
Rated supply voltage	3 V	3 V
Processing package description	PLASTIC, DIP-20	PLASTIC, DIP-20
state	ACTIVE	ACTIVE
Craftsmanship	CMOS	CMOS
packaging shape	RECTANGULAR	RECTANGULAR
Package Size	IN-LINE	IN-LINE
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal spacing	2.54 mm	2.54 mm
terminal coating	TIN LEAD	TIN LEAD
Terminal location	DUAL	DUAL
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	MILITARY	MILITARY
series	HC/UH	HC/UH
Logic IC type	D FLIP-FLOP	D FLIP-FLOP
Number of digits	8	8
Output polarity	TRUE	TRUE
propagation delay TPD	220 ns	220 ns
Trigger type	POSITIVE EDGE	POSITIVE EDGE
Max-Min frequency	24 MHz	24 MHz

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