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MC74HC273

Description
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
Categorysemiconductor    logic   
File Size116KB,7 Pages
ManufacturerMotorola ( NXP )
Websitehttps://www.nxp.com
Download Datasheet Parametric Compare View All

MC74HC273 Overview

HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20

MC74HC273 Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals20
Maximum operating temperature125 Cel
Minimum operating temperature-55 Cel
Maximum supply/operating voltage6 V
Minimum supply/operating voltage2 V
Rated supply voltage3 V
Processing package descriptionPLASTIC, DIP-20
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeIN-LINE
Terminal formTHROUGH-HOLE
Terminal spacing2.54 mm
terminal coatingTIN LEAD
Terminal locationDUAL
Packaging MaterialsPLASTIC/EPOXY
Temperature levelMILITARY
seriesHC/UH
Logic IC typeD FLIP-FLOP
Number of digits8
Output polarityTRUE
propagation delay TPD220 ns
Trigger typePOSITIVE EDGE
Max-Min frequency24 MHz
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
The MC54/74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of eight D flip–flops with common Clock and Reset
inputs. Each flip–flop is loaded with a low–to–high transition of the Clock
input. Reset is asynchronous and active low.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 264 FETs or 66 Equivalent Gates
MC54/74HC273A
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
20
1
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
DT SUFFIX
TSSOP PACKAGE
CASE 948E–02
20
1
20
1
ORDERING INFORMATION
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
19
11
2
5
6
9
12
15
16
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
MC74HCXXXADT
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
Ceramic
Plastic
SOIC
TSSOP
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
PIN ASSIGNMENT
RESET
Q0
D0
D1
Q1
Q2
D2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CLOCK
RESET
1
PIN 20 = VCC
PIN 10 = GND
D3
Q3
GND
10/95
©
Motorola, Inc. 1995
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Design Criteria
Value
66
Units
ea
ns
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
1.5
5.0
µW
pJ
.0075
* Equivalent to a two–input NAND gate.
3–1
REV 6
FUNCTION TABLE
Inputs
Reset
L
H
H
H
H
Clock
X
D
X
H
L
X
X
Output
Q
L
H
L
No Change
No Change
L

MC74HC273 Related Products

MC74HC273 74273
Description HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20 HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20
Number of functions 1 1
Number of terminals 20 20
Maximum operating temperature 125 Cel 125 Cel
Minimum operating temperature -55 Cel -55 Cel
Maximum supply/operating voltage 6 V 6 V
Minimum supply/operating voltage 2 V 2 V
Rated supply voltage 3 V 3 V
Processing package description PLASTIC, DIP-20 PLASTIC, DIP-20
state ACTIVE ACTIVE
Craftsmanship CMOS CMOS
packaging shape RECTANGULAR RECTANGULAR
Package Size IN-LINE IN-LINE
Terminal form THROUGH-HOLE THROUGH-HOLE
Terminal spacing 2.54 mm 2.54 mm
terminal coating TIN LEAD TIN LEAD
Terminal location DUAL DUAL
Packaging Materials PLASTIC/EPOXY PLASTIC/EPOXY
Temperature level MILITARY MILITARY
series HC/UH HC/UH
Logic IC type D FLIP-FLOP D FLIP-FLOP
Number of digits 8 8
Output polarity TRUE TRUE
propagation delay TPD 220 ns 220 ns
Trigger type POSITIVE EDGE POSITIVE EDGE
Max-Min frequency 24 MHz 24 MHz

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