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74ABT377

Description
Octal D-Type Flip-Flop with Clock Enable
File Size101KB,9 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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74ABT377 Overview

Octal D-Type Flip-Flop with Clock Enable

74ABT377 Octal D-Type Flip-Flop with Clock Enable
January 1993
Revised November 1999
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s
Clock enable for address and data synchronization
applications
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
See ABT273 for master reset version
s
See ABT373 for transparent latch version
s
See ABT374 for 3-STATE version
s
Output sink capability of 64 mA, source capability
of 32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT377CSC
74ABT377CSJ
74ABT377CMSA
74ABT377CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CE
CP
Q
0
–Q
7
Descriptions
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
Truth Table
Operating Mode
CP
Load “1”
Load “0”
Hold
(Do Nothing)
Inputs
Output
D
n
h
I
X
X
Q
n
H
L
No Change
No Change



X
CE
I
I
h
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
h
=
HIGH Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
I
=
LOW Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition

© 1999 Fairchild Semiconductor Corporation
DS011550
www.fairchildsemi.com

74ABT377 Related Products

74ABT377 74ABT377CMSA 74ABT377CSC 74ABT377CMTC 74ABT377CSJ
Description Octal D-Type Flip-Flop with Clock Enable Octal D-Type Flip-Flop with Clock Enable Octal D-Type Flip-Flop with Clock Enable Octal D-Type Flip-Flop with Clock Enable Octal D-Type Flip-Flop with Clock Enable
Is it Rohs certified? - conform to conform to incompatible conform to
Maker - Fairchild Fairchild Fairchild Fairchild
Parts packaging code - SSOP SOIC TSSOP SOIC
package instruction - 5.30 MM, EIAJ TYPE2, SSOP-20 SOP, SOP20,.4 TSSOP, TSSOP20,.25 5.30 MM, EIAJ TYPE2, SOP-20
Contacts - 20 20 20 20
Reach Compliance Code - compliant unknown compli compli
Other features - WITH HOLD MODE WITH HOLD MODE WITH HOLD MODE WITH HOLD MODE
series - ABT ABT ABT ABT
JESD-30 code - R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20
JESD-609 code - e3 e3 e0 e3
length - 7.2 mm 12.8 mm 6.5 mm 12.6 mm
Load capacitance (CL) - 50 pF 50 pF 50 pF 50 pF
Logic integrated circuit type - D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
MaximumI(ol) - 0.064 A 0.064 A 0.064 A 0.064 A
Humidity sensitivity level - 1 1 - 1
Number of digits - 8 8 8 8
Number of functions - 1 1 1 1
Number of terminals - 20 20 20 20
Maximum operating temperature - 85 °C 85 °C 85 °C 85 °C
Minimum operating temperature - -40 °C -40 °C -40 °C -40 °C
Output polarity - TRUE TRUE TRUE TRUE
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code - SSOP SOP TSSOP SOP
Encapsulate equivalent code - SSOP20,.3 SOP20,.4 TSSOP20,.25 SOP20,.3
Package shape - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form - SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE
Peak Reflow Temperature (Celsius) - 260 260 - 260
power supply - 5 V 5 V 5 V 5 V
Maximum supply current (ICC) - 30 mA 30 mA 30 mA 30 mA
propagation delay (tpd) - 6.8 ns 6.8 ns 6.8 ns 6.8 ns
Certification status - Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height - 2.05 mm 2.65 mm 1.2 mm 2.1 mm
Maximum supply voltage (Vsup) - 5.5 V 5.5 V 5.5 V 5.5 V
Minimum supply voltage (Vsup) - 4.5 V 4.5 V 4.5 V 4.5 V
Nominal supply voltage (Vsup) - 5 V 5 V 5 V 5 V
surface mount - YES YES YES YES
technology - BICMOS BICMOS BICMOS BICMOS
Temperature level - INDUSTRIAL INDUSTRIAL INDUSTRIAL INDUSTRIAL
Terminal surface - Matte Tin (Sn) Matte Tin (Sn) Tin/Lead (Sn/Pb) Matte Tin (Sn)
Terminal form - GULL WING GULL WING GULL WING GULL WING
Terminal pitch - 0.65 mm 1.27 mm 0.65 mm 1.27 mm
Terminal location - DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature - NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED
Trigger type - POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
width - 5.3 mm 7.5 mm 4.4 mm 5.3 mm
minfmax - 150 MHz 150 MHz 150 MHz 150 MHz
Base Number Matches - 1 1 1 1

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