74ABT377 Octal D-Type Flip-Flop with Clock Enable
January 1993
Revised November 1999
74ABT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The ABT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop’s Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s
Clock enable for address and data synchronization
applications
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
See ABT273 for master reset version
s
See ABT373 for transparent latch version
s
See ABT374 for 3-STATE version
s
Output sink capability of 64 mA, source capability
of 32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time less than enable time to avoid bus
contention
Ordering Code:
Order Number
74ABT377CSC
74ABT377CSJ
74ABT377CMSA
74ABT377CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
0
–D
7
CE
CP
Q
0
–Q
7
Descriptions
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
Truth Table
Operating Mode
CP
Load “1”
Load “0”
Hold
(Do Nothing)
Inputs
Output
D
n
h
I
X
X
Q
n
H
L
No Change
No Change
X
CE
I
I
h
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Immaterial
=
LOW-to-HIGH Clock Transition
h
=
HIGH Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
I
=
LOW Voltage Level one setup time prior to the
LOW-to-HIGH Clock Transition
© 1999 Fairchild Semiconductor Corporation
DS011550
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74ABT377
Absolute Maximum Ratings
(Note 1)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
V
CC
Pin Potential to Ground Pin
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Any Output
in the Disabled or
Power-OFF State
in the HIGH State
Current Applied to Output
in LOW State (Max)
DC Latchup Source Current
(Across Comm Operating Range)
Over Voltage Latchup
V
CC
+
4.5V
Twice the rated I
OL
(mA)
−500
mA
−0.5V
to
+4.75V
−0.5V
to V
CC
−65°C
to
+150°C
−55°C
to
+125°C
−55°C
to
+150°C
−0.5V
to
+7.0V
−0.5V
to
+7.0V
−30
mA to
+5.0
mA
Recommended Operating
Conditions
Free Air Ambient Temperature
Supply Voltage
Minimum Input Edge Rate (∆V/∆t)
Data Input
Enable Input
50 mV/ns
20 mV/ns
−40°C
to
+85°C
+4.5V
to
+5.5V
Note 1:
Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2:
Either voltage limit or current limit is sufficient to protect inputs
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
CD
V
OH
V
OL
I
IH
I
BVI
I
IL
V
ID
I
OS
I
CEX
I
CCH
I
CCL
I
CCT
Parameter
Input HIGH Voltage
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Current
Input HIGH Current
Breakdown Test
Input LOW Current
Input Leakage Test
Output Short-Circuit Current
Output HIGH Leakage Current
Power Supply Current
Power Supply Current
Maximum I
CC
/Input
Outputs Enabled
1.5
I
CCD
Dynamic I
CC
No Load
0.3
mA
mA/
MHz
Note 3:
Guaranteed but not tested.
Note 4:
For 8 bits toggling, I
CCD
<
0.5 mA/MHz.
Min
2.0
Typ
Max
Units
V
V
CC
Conditions
Recognized HIGH Signal
Recognized LOW Signal
0.8
−1.2
2.5
2.0
0.55
1
1
7
−1
−1
4.75
−100
−275
50
50
30
V
V
V
V
µA
µA
µA
V
mA
µA
µA
mA
Min
Min
Min
Max
Max
Max
0.0
Max
Max
Max
Max
Max
Max
I
IN
= −18
mA
I
OH
= −3
mA
I
OH
= −32
mA
I
OL
=
64 mA
V
IN
=
2.7V (Note 3)
V
IN
=
V
CC
V
IN
=
7.0V
V
IN
=
0.5V (Note 3)
V
IN
=
0.0V
I
ID
=
1.9
µA
All Other Pins Grounded
V
OUT
=
0.0V
V
OUT
=
V
CC
All Outputs HIGH
All Outputs LOW
V
I
=
V
CC
−
2.1V
Data Input V
I
=
V
CC
−
2.1V
All Others at V
CC
or GND
Outputs Open (Note 4)
One bit Toggling, 50% Duty Cycle
3
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74ABT377
AC Loading
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
Input Pulse Requirements
Amplitude
3.0V
Rep. Rate
1 MHz
t
W
500 ns
t
r
2.5 ns
FIGURE 2. V
M
=
1.5V
t
f
2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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