SN74LS113AJS datasheet, PDF - EEWORLD Datasheet

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SN74LS113AJS: DescriptionLS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14; Categorylogic logic; File Size53KB，2 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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SN74LS113AJS Overview

LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14

SN74LS113AJS Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Motorola ( NXP )
Parts packaging code	DIP
package instruction	DIP, DIP14,.3
Contacts	14
Reach Compliance Code	unknown
series	LS
JESD-30 code	R-GDIP-T14
JESD-609 code	e0
length	19.495 mm
Logic integrated circuit type	J-K FLIP-FLOP
Number of digits	2
Number of functions	2
Number of terminals	14
Maximum operating temperature	70 °C
Minimum operating temperature
Output polarity	COMPLEMENTARY
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
propagation delay (tpd)	20 ns
Certification status	Not Qualified
Maximum seat height	5.08 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	4.75 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Trigger type	NEGATIVE EDGE
width	7.62 mm
minfmax	45 MHz
Base Number Matches	1

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SN74LS113AJS Related Products

	SN74LS113AJS	SN74LS113ANS
Description	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
Is it Rohs certified?	incompatible	incompatible
Maker	Motorola ( NXP )	Motorola ( NXP )
package instruction	DIP, DIP14,.3	DIP, DIP14,.3
Reach Compliance Code	unknown	unknown
series	LS	LS
JESD-30 code	R-GDIP-T14	R-PDIP-T14
JESD-609 code	e0	e0
length	19.495 mm	18.86 mm
Logic integrated circuit type	J-K FLIP-FLOP	J-K FLIP-FLOP
Number of digits	2	2
Number of functions	2	2
Number of terminals	14	14
Maximum operating temperature	70 °C	70 °C
Output polarity	COMPLEMENTARY	COMPLEMENTARY
Package body material	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY
encapsulated code	DIP	DIP
Encapsulate equivalent code	DIP14,.3	DIP14,.3
Package shape	RECTANGULAR	RECTANGULAR
Package form	IN-LINE	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	5 V	5 V
propagation delay (tpd)	20 ns	20 ns
Certification status	Not Qualified	Not Qualified
Maximum seat height	5.08 mm	5.08 mm
Maximum supply voltage (Vsup)	5.25 V	5.25 V
Minimum supply voltage (Vsup)	4.75 V	4.75 V
Nominal supply voltage (Vsup)	5 V	5 V
surface mount	NO	NO
technology	TTL	TTL
Temperature level	COMMERCIAL	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
Trigger type	NEGATIVE EDGE	NEGATIVE EDGE
width	7.62 mm	7.62 mm
minfmax	45 MHz	45 MHz
Base Number Matches	1	1

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