EEWORLDEEWORLDEEWORLD

Part Number

Search

74F673ASC

Description
F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24
Categorylogic    logic   
File Size67KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
Download Datasheet Parametric Compare View All

74F673ASC Online Shopping

Suppliers Part Number Price MOQ In stock  
74F673ASC - - View Buy Now

74F673ASC Overview

F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24

74F673ASC Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instruction0.300 INCH, PLASTIC, MS-013, SOIC-24
Contacts24
Reach Compliance Codecompliant
Other featuresPARALLEL OUTPUT IS REGISTERED
Counting directionRIGHT
seriesF/FAST
JESD-30 codeR-PDSO-G24
JESD-609 codee3
length15.4 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Maximum Frequency@Nom-Sup85000000 Hz
Humidity sensitivity level1
Number of digits16
Number of functions1
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP24,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)172 mA
propagation delay (tpd)12 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeNEGATIVE EDGE
width7.5 mm
minfmax85 MHz
Base Number Matches1
74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
April 1988
Revised August 1999
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a 3-
STATE serial output. In the Serial-Out mode, the data recir-
culates in the shift register. By means of a separate clock,
the contents of the shift register are transferred to the stor-
age register for parallel outputting. The contents of the stor-
age register can also be parallel loaded back into the shift
register. A HIGH signal on the Chip Select input prevents
both shifting and parallel transfer. The storage register may
be cleared via STMR.
Features
s
Serial-to-parallel converter
s
16-bit serial I/O shift register
s
16-bit parallel-out storage register
s
Recirculating serial shifting
s
Recirculating parallel transfer
s
Common serial data I/O pin
s
Slim 24 lead package
Ordering Code:
Order Number
74F673ASC
74F673APC
74F673ASPC
Package Number
M24B
N24A
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
DS009585
www.fairchildsemi.com

74F673ASC Related Products

74F673ASC 74F673A 74F673APC 74F673ASPC
Description F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24
series F/FAST F/FAST F/FAST F/FAST
Number of digits 16 16 16 16
Number of functions 1 1 1 1
Number of terminals 24 24 24 24
Maximum operating temperature 70 °C 70 Cel 70 °C 70 °C
Output polarity TRUE TRUE TRUE TRUE
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form GULL WING THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE
Terminal location DUAL DUAL DUAL DUAL
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
Is it Rohs certified? conform to - conform to conform to
Maker Fairchild - Fairchild Fairchild
Parts packaging code SOIC - DIP DIP
package instruction 0.300 INCH, PLASTIC, MS-013, SOIC-24 - 0.600 INCH, SLIM, PLASTIC, MS-011, DIP-24 DIP, DIP24,.3
Contacts 24 - 24 24
Reach Compliance Code compliant - compli compli
Other features PARALLEL OUTPUT IS REGISTERED - PARALLEL OUTPUT IS REGISTERED PARALLEL OUTPUT IS REGISTERED
Counting direction RIGHT - RIGHT RIGHT
JESD-30 code R-PDSO-G24 - R-PDIP-T24 R-PDIP-T24
JESD-609 code e3 - e3 e3
length 15.4 mm - 31.915 mm 31.915 mm
Load capacitance (CL) 50 pF - 50 pF 50 pF
Logic integrated circuit type SERIAL IN PARALLEL OUT - SERIAL IN PARALLEL OUT SERIAL IN PARALLEL OUT
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code SOP - DIP DIP
Encapsulate equivalent code SOP24,.4 - DIP24,.6 DIP24,.3
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE - IN-LINE IN-LINE
Peak Reflow Temperature (Celsius) 260 - NOT SPECIFIED NOT SPECIFIED
power supply 5 V - 5 V 5 V
Maximum supply current (ICC) 172 mA - 172 mA 172 mA
propagation delay (tpd) 12 ns - 12 ns 12 ns
Certification status Not Qualified - Not Qualified Not Qualified
Maximum seat height 2.65 mm - 5.334 mm 5.08 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V 5 V
surface mount YES - NO NO
technology TTL - TTL TTL
Terminal surface Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn)
Terminal pitch 1.27 mm - 2.54 mm 2.54 mm
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
width 7.5 mm - 15.24 mm 7.62 mm
minfmax 85 MHz - 85 MHz 85 MHz
Base Number Matches 1 - 1 1
LC parallel resonance frequency selection circuit
Working principle: 1. When powered on, C3, L1 and L2 form an LC parallel resonant circuit, generating numerous small signal sources. 2. Characteristics of LC parallel resonant circuit: For the resonan...
小魏哥哥 Switching Power Supply Study Group
Show off the slimming tea I bought with E coins
Although the work is good, I still need to continue to lose weight and not let overtime work defeat me!...
平行电 Talking
(Wireless Charging Electric Car) Second Prize of Sichuan Province, Topic C, Chengdu College of University of Electronic Science and Technology of China
[align=left][font=微软雅黑, "][size=14px][size=3][color=#000000]This time we bring a wireless charging electric car. We use the transmitting and receiving ends of the coil for wireless charging, and the r...
sigma Electronics Design Contest
How to set external wake-up interrupt in s3c6410 wince6
As title...
suweibus Embedded System
My Explanation for “2008”
[i=s]This post was last edited by paulhyde on 2014-9-15 09:17[/i] [size=5] 2008, I find this number quite interesting... First of all, the first digit "2" means two, and then there are two "0"s after ...
open82977352 Electronics Design Contest

Technical ResourceMore

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 858  1373  2283  2425  2027  18  28  46  49  41 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号