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74F673ASPC

Description
F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24
Categorylogic    logic   
File Size67KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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74F673ASPC Overview

F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24

74F673ASPC Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP24,.3
Contacts24
Reach Compliance Codecompli
Other featuresPARALLEL OUTPUT IS REGISTERED
Counting directionRIGHT
seriesF/FAST
JESD-30 codeR-PDIP-T24
JESD-609 codee3
length31.915 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeSERIAL IN PARALLEL OUT
Maximum Frequency@Nom-Su85000000 Hz
Number of digits16
Number of functions1
Number of terminals24
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP24,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)172 mA
propagation delay (tpd)12 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeNEGATIVE EDGE
width7.62 mm
minfmax85 MHz
Base Number Matches1
74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
April 1988
Revised August 1999
74F673A
16-Bit Serial-In, Serial/Parallel-Out Shift Register
General Description
The 74F673A contains a 16-bit serial-in, serial-out shift
register and a 16-bit Parallel-Out storage register. A single
pin serves either as an input for serial entry or as a 3-
STATE serial output. In the Serial-Out mode, the data recir-
culates in the shift register. By means of a separate clock,
the contents of the shift register are transferred to the stor-
age register for parallel outputting. The contents of the stor-
age register can also be parallel loaded back into the shift
register. A HIGH signal on the Chip Select input prevents
both shifting and parallel transfer. The storage register may
be cleared via STMR.
Features
s
Serial-to-parallel converter
s
16-bit serial I/O shift register
s
16-bit parallel-out storage register
s
Recirculating serial shifting
s
Recirculating parallel transfer
s
Common serial data I/O pin
s
Slim 24 lead package
Ordering Code:
Order Number
74F673ASC
74F673APC
74F673ASPC
Package Number
M24B
N24A
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
IEEE/IEC
Connection Diagram
© 1999 Fairchild Semiconductor Corporation
DS009585
www.fairchildsemi.com

74F673ASPC Related Products

74F673ASPC 74F673A 74F673APC 74F673ASC
Description F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24 F/FAST SERIES, 16-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP24
series F/FAST F/FAST F/FAST F/FAST
Number of digits 16 16 16 16
Number of functions 1 1 1 1
Number of terminals 24 24 24 24
Maximum operating temperature 70 °C 70 Cel 70 °C 70 °C
Output polarity TRUE TRUE TRUE TRUE
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form THROUGH-HOLE THROUGH-HOLE THROUGH-HOLE GULL WING
Terminal location DUAL DUAL DUAL DUAL
Trigger type NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE NEGATIVE EDGE
Is it Rohs certified? conform to - conform to conform to
Maker Fairchild - Fairchild Fairchild
Parts packaging code DIP - DIP SOIC
package instruction DIP, DIP24,.3 - 0.600 INCH, SLIM, PLASTIC, MS-011, DIP-24 0.300 INCH, PLASTIC, MS-013, SOIC-24
Contacts 24 - 24 24
Reach Compliance Code compli - compli compliant
Other features PARALLEL OUTPUT IS REGISTERED - PARALLEL OUTPUT IS REGISTERED PARALLEL OUTPUT IS REGISTERED
Counting direction RIGHT - RIGHT RIGHT
JESD-30 code R-PDIP-T24 - R-PDIP-T24 R-PDSO-G24
JESD-609 code e3 - e3 e3
length 31.915 mm - 31.915 mm 15.4 mm
Load capacitance (CL) 50 pF - 50 pF 50 pF
Logic integrated circuit type SERIAL IN PARALLEL OUT - SERIAL IN PARALLEL OUT SERIAL IN PARALLEL OUT
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code DIP - DIP SOP
Encapsulate equivalent code DIP24,.3 - DIP24,.6 SOP24,.4
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR
Package form IN-LINE - IN-LINE SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED 260
power supply 5 V - 5 V 5 V
Maximum supply current (ICC) 172 mA - 172 mA 172 mA
propagation delay (tpd) 12 ns - 12 ns 12 ns
Certification status Not Qualified - Not Qualified Not Qualified
Maximum seat height 5.08 mm - 5.334 mm 2.65 mm
Maximum supply voltage (Vsup) 5.5 V - 5.5 V 5.5 V
Minimum supply voltage (Vsup) 4.5 V - 4.5 V 4.5 V
Nominal supply voltage (Vsup) 5 V - 5 V 5 V
surface mount NO - NO YES
technology TTL - TTL TTL
Terminal surface Matte Tin (Sn) - Matte Tin (Sn) Matte Tin (Sn)
Terminal pitch 2.54 mm - 2.54 mm 1.27 mm
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED
width 7.62 mm - 15.24 mm 7.5 mm
minfmax 85 MHz - 85 MHz 85 MHz
Base Number Matches 1 - 1 1

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