AGLP125-V2FCSG289ES datasheet, PDF

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AGLP125-V2FCSG289ES: DescriptionFPGA, 3120 CLBS, 125000 GATES, PBGA289; Categorysemiconductor Programmable logic devices; File Size498KB，14 Pages; ManufacturerActel; Websitehttp://www.actel.com/

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AGLP125-V2FCSG289ES Overview

FPGA, 3120 CLBS, 125000 GATES, PBGA289

AGLP125-V2FCSG289ES Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	289
Maximum operating temperature	85 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	1.58 V
Minimum supply/operating voltage	1.42 V
Rated supply voltage	1.5 V
Processing package description	14 X 14 MM, 1.2 MM HEIGHT, 0.8 MM PITCH, ROHS COMPLIANT, CSP-289
Lead-free	Yes
EU RoHS regulations	Yes
state	ACTIVE
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	GRID ARRAY, THIN PROFILE, FINE PITCH
surface mount	Yes
Terminal form	BALL
Terminal spacing	0.8000 mm
terminal coating	NOT SPECIFIED
Terminal location	BOTTOM
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
organize	3120 CLBS, 125000 GATES
Number of configurable logic modules	3120
Programmable logic type	FIELD PROGRAMMABLE GATE ARRAY
Number of equivalent gate circuits	125000

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v1.3

IGLOO PLUS Low-Power Flash FPGAs

with Flash*Freeze Technology

Features and Benefits

Low Power

•

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

5 µW Power Consumption in Flash*Freeze Mode

Low-Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Configurable Hold Previous State, Tristate, HIGH, or LOW

State per I/O in Flash*Freeze Mode

• Easy Entry To / Exit From Ultra-Low-Power Flash*Freeze Mode

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

Advanced I/O

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—4 Banks per Chip on All

IGLOO

PLUS Devices

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

• Selectable Schmitt Trigger Inputs

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Small-Footprint Packages across the IGLOO

PLUS Family

†

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Feature Rich

• 30 k to 125 k System Gates

• Up to 36 kbits of True Dual-Port SRAM

• Up to 212 User I/Os

Reprogrammable Flash Technology

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design When Powered Off

Clock Conditioning Circuit (CCC) and PLL

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

†

• FlashLock

to Secure FPGA Contents

Embedded Memory

• 1 kbit of FlashROM User Nonvolatile Memory

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

†

• True Dual-Port SRAM (except ×18)

†

AGLP030

30 k

256

792

–

120

CS201, CS289

VQ128

AGLP060

60 k

512

1,584

Yes

157

CS201, CS289

VQ176

AGLP125

125 k

1,024

3,120

Yes

212

CS281, CS289

Table 1-1 •

IGLOO PLUS Product Family

IGLOO PLUS Devices

System Gates

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

Secure (AES) ISP

FlashROM Bits

Integrated PLL in CCCs

VersaNet Globals

I/O Banks

Maximum User I/Os

Package Pins

Notes:

1. AGLP060 in CS201 does not support the PLL.

2. Six chip (main) and twelve quadrant global networks are available for AGLP060 and AGLP125.

† The AGLP030 device does not support this feature.

December 2008

1 – IGLOO PLUS Device Family Overview

General Description

The IGLOO PLUS family of flash FPGAs, based on a 130 nm flash process, offers the lowest power

FPGA, a single-chip solution, small-footprint packages, reprogrammability, and an abundance of

advanced features.

The Flash*Freeze technology used in IGLOO PLUS devices enables entering and exiting an ultra-

low-power mode that consumes as little as 5 µW while retaining the design information, SRAM

content, registers, and I/O states. Flash*Freeze technology simplifies power management through

I/O and clock management with rapid recovery to operation mode.

The Low Power Active capability (static idle) allows for ultra-low-power consumption while the

IGLOO PLUS device is completely functional in the system. This allows the IGLOO PLUS device to

control system power management based on external inputs (e.g., scanning for keyboard stimulus)

while consuming minimal power.

Nonvolatile flash technology gives IGLOO PLUS devices the advantage of being a secure, low-

power, single-chip solution that is live at power-up (LAPU). IGLOO PLUS is reprogrammable and

offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

IGLOO PLUS devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well

as clock conditioning circuitry based on an integrated phase-locked loop (PLL). IGLOO PLUS devices

have up to 125 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 212

user I/Os. The AGLP030 devices have no PLL or RAM support.

Flash*Freeze Technology

The IGLOO PLUS device offers unique Flash*Freeze technology, allowing the device to enter and

exit ultra-low-power Flash*Freeze mode. IGLOO PLUS devices do not need additional components

to turn off I/Os or clocks while retaining the design information, SRAM content, registers, and I/O

states. Flash*Freeze technology is combined with in-system programmability, which enables users

to quickly and easily upgrade and update their designs in the final stages of manufacturing or in

the field. The ability of IGLOO PLUS V2 devices to support a wide range of core and I/O voltages

(1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total

system power.

During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state,

tristate, or set as HIGH or LOW.

The availability of low-power modes, combined with reprogrammability, a single-chip and single-

voltage solution, and availability of small-footprint, high-pin-count packages, make IGLOO PLUS

devices the best fit for portable electronics.

Flash Advantages

Low Power

IGLOO PLUS devices exhibit power characteristics similar to those of an ASIC, making them an ideal

choice for power-sensitive applications. IGLOO PLUS devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

IGLOO PLUS devices also have low dynamic power consumption to further maximize power savings;

power is even further reduced by the use of a 1.2 V core voltage.

Low dynamic power consumption, combined with low static power consumption and Flash*Freeze

technology, gives the IGLOO PLUS device the lowest total system power offered by any FPGA.

v1.3

1-1

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