and other passive components that are traditionally
The P2008A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The P2008A modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Product Description
The P2008A is a versatile spread spectrum frequency
modulator designed specifically for digital camera and
other digital video and imaging applications. The P2008A
reduces electromagnetic interference (EMI) at the clock
source, allowing system wide reduction of EMI of down
stream clock and data dependent signals. The P2008A
allows significant system cost savings by reducing the
Applications
The P2008A is targeted towards cable, xDSL, fax
modem, set-top box, USB controller, DSC, and other
embedded systems.
Block Diagram
VDD
SR0 SSON#
DIV2
Modulation
XIN/CLKIN
XOUT
Feedback
Divider
Crystal
Oscillator
Frequency
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
July 2005
rev 1.3
Pin Configuration
XIN/ CLKIN
XOUT
DIV2
VSS
1
2
3
4
8
7
6
5
P2008A
VDD
SR0
ModOUT
SSON#
P2008A
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLKIN
XOUT
DIV2
VSS
SSON#
ModOUT
SR0
VDD
Type
I
O
I
P
I
O
I
P
Description
Crystal connection or external reference frequency input. This pin has dual
functions. It can be connected either to an external crystal or an external
reference clock.
Crystal connection. If using an external reference, this pin must be left
unconnected.
Digital logic input used to select normal output mode or divide-by-two output
mode. When this pin is HIGH, the frequency of the output clock is the same as the
input clock frequency. When it is tied low, the output frequency is half the input
clock frequency. This pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH.
This pin has an internal pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range (Refer
Modulation Output and
Spreading Range Selection Table.)
This pin has an internal pull-up resistor.
Power supply for the entire chip
Modulation Output and Spreading Selection (ModOUT = XIN/CLKIN)
Output Frequency Range DIV2 = 1
8MHz
0
1
± 2.2%
± 3.2%
12MHz
± 1.8%
± 2.5%
16MHz
± 1.2%
± 2.0%
20MHz
± 1.1%
± 1.6%
24MHz
± 1.0%
± 1.4%
28MHz
± 0.9%
± 1.25%
32MHz
± 0.8%
± 0.15%
(XIN/CLKIN/20) * 62.5 KHz
SR0
Modulation Rate
Modulation Output and Spreading Selection (ModOUT = ½ XIN/CLKIN)
Output Frequency Range DIV2 = 0
4MHz
0
1
± 2.0%
± 3.2%
6MHz
± 1.8%
± 2.6%
8MHz
± 1.2%
± 2.0%
10MHz
± 1.1%
± 1.6%
12MHz
± 1.0%
± 1.4%
14MHz
± 0.9%
± 1.25%
16MHz
± 0.8%
± 0.15%
(XIN/CLKIN/20) * 62.5 KHz
SR0
Modulation Rate
General purpose EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 9
July 2005
rev 1.3
Spread Spectrum
P2008A
The
Modulation Output and Spreading Selection Tables
illustrate the two possible spread spectrum options. The optimal
setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a
percentage deviation of the center frequency (Note: The center frequency is the frequency of the external reference input on
XIN/CLKIN, Pin1).
Example:
The P2008A is designed for communications, digital video and imaging applications. It is not only optimized for operation in
the 4MHz – 32MHz range, but its output frequency can be extended down to one half of the input clock frequency using the
divide-by-two feature. This feature extends low frequency as low as to 2MHz. Setting Pin 3 low (DIV2 = 0; Divide-by-two
mode) sets the output frequency (ModOUT) to half the frequency of the input clock (XIN/CLKIN). This is a simple way to
generate a spread spectrum modulated low frequency clock when only a higher frequency signal is available. If you want the
output frequency to be the same as the input, you can either set DIV2=1 or leave it unconnected.
Selecting the P2008A’s spread options is a matter of either setting SR0=1 or SR0=0. Setting SR0=0 set as a lower
modulation spread, while setting it to 1 introduces a wider spectral spread in the output clock.
Refer Modulation output and
Spreading Selections Tables.
The example given in the figure below shows the device set to the divide-by-two mode
(DIV2=0) with a lower spectrum range (SR0=0). The versatility provided by allowing both clock division and spread spectrum
on one chip is already proving to be a popular solution among leading system manufacturers.
P2008A Application Schematic
+3.3V
8.832MHz Crystal
1
XIN/CLKIN
XOUT
DIV2
VSS
VDD
SR0
Mod OUT
SSON#
8
2
7
0.1µF
6
3
4
5
P2008A
Modulated 4.416MHz is
connected to CLK input
pin of the system
General purpose EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 9
July 2005
rev 1.3
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
P2008A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
(pull-up resistors on inputs SR0 and DIV2)
Input high current (pull-down resistor on input SSON#)
XOUT Output Low Current (@ 0.4V, VDD = 3.3V)
XOUT Output High Current (@ 2.5V, VDD = 3.3V)
Output low voltage (VDD = 3.3V, I
OL
= 10mA)
Output high voltage (VDD = 3.3V, I
OH
= 10mA)
Dynamic supply current normal mode
(3.3V, and 15pF loading)
Static supply current standby mode
Operating voltage
Power up time (first locked clock cycle after power up)
Clock output impedance
Parameter
Min
VSS – 0.3
2.0
-
-
-
-
-
2.5
6.0
-
3.0
-
-
Typ
-
-
-
-
3
3
-
-
7.0
0.6
3.3
0.18
50
Max
0.8
VDD + 0.3
-35
35
-
-
0.4
-
8.3
-
3.6
-
-
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
V
mS
Ω
General purpose EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 9
July 2005
rev 1.3
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
*
t
HL
*
t
JC
t
D
Input frequency
Output frequency
DIV2 =0
DIV2 =1
P2008A
Parameter
Min
4
2
4
0.7
0.6
-
45
Typ
20
10
20
0.9
0.8
-
50
Max
32
16
32
1.1
1.0
360
55
Unit
MHz
MHz
nS
nS
pS
%
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
*t
LH
and t
HL
are measured into a capacitive load of 15pF
General purpose EMI Reduction IC
Notice: The information in this document is subject to change without notice.
[i=s]This post was last edited by Chen Shaohua on 2018-6-21 22:06[/i] The information in this post is all reprinted and summarized. Friends can also send your information back to me and I will update ...
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