INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT597
8-bit shift register with input
flip-flops
Product specification
File under Integrated Circuits, IC06
December 1990
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
FEATURES
•
8-bit parallel storage register inputs
•
Shift register has direct overriding load and clear
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
74HC/HCT597
The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
SH
CP
to Q
ST
CP
to Q
PL to Q
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency SH
CP
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
17
25
21
96
3.5
29
20
29
26
83
3.5
32
ns
ns
ns
MHz
pF
pF
HCT
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
PIN DESCRIPTION
PIN NO.
8
9
10
11
12
13
14
15, 1, 2, 3, 4, 5, 6, 7
16
SYMBOL
GND
Q
MR
SH
CP
ST
CP
PL
D
S
D
0
to D
7
V
CC
NAME AND FUNCTION
ground (0 V)
serial data output
asynchronous reset input (active LOW)
74HC/HCT597
shift clock input (LOW-to-HIGH, edge-triggered)
storage clock input (LOW-to-HIGH, edge-triggered)
parallel load input (active LOW)
serial data input
parallel data inputs
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.4 Functional diagram.
FUNCTION TABLE
ST
CP
↑
↑
no clock edge
X
X
X
Notes
1. H
L
X
↑
= HIGH voltage level
= LOW voltage level
= don’t care
= LOW-to-HIGH CP transition
SH
CP
X
X
X
X
X
↑
PL
X
L
L
L
H
H
MR
X
H
H
L
L
H
FUNCTION
data loaded to input latches
data loaded from inputs to shift register
data transferred from input flip-flops to shift register
invalid logic, state of shift register indeterminate when signals removed
shift register cleared
shift register clocked Q
n
= Q
n
−
1
, Q
0
= D
S
December 1990
4
Philips Semiconductors
Product specification
8-bit shift register with input flip-flops
74HC/HCT597
Fig.5 Logic diagram.
December 1990
5
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