INTEGRATED CIRCUITS
74F377A
Octal D-type flip-flop with enable
Product specification
IC15 Data Handbook
1996 Mar 12
Philips
Semiconductors
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
FEATURES
High states)
•
High impedance inputs for reduced loading (20µA in Low and
•
Ideal for addressable register applications
•
Enable for address and data synchronization applications
•
Eight edge–triggered D–type flip–flops
•
Buffered common clock
•
See ’F273A for Master Reset version
•
See ’F373 for transparent latch version
•
See ’F374 for 3–State version
TYPE
74F377A
TYPICAL f
MAX
165MHz
DESCRIPTION
The 74F377A has 8 edge-triggered D-type flip-flops with individual D
inputs and Q outputs. The common buffered clock (CP) input loads
all flip-flops simultaneously when the Enable (E) input is Low.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
The E input must be stable one setup time prior to the Low-to-High
clock transition for predictable operation.
TYPICAL SUPPLY CURRENT (TOTAL)
29mA
ORDERING INFORMATION
PACKAGES
20–pin plastic DIP
20–pin plastic SOL
COMMERCIAL RANGE
V
CC
= 5V±10%; T
amb
= 0°C to +70°C
N74F377AN
N74F377AD
PKG. DWG. #
SOT146-1
SOT163-1
INPUT AND OUTPUT LOADING AND FAN–OUT TABLE
PINS
D0 – D7
CP
E
Q0 – Q7
Data inputs
Clock pulse input (active rising edge)
Enable input (active–Low)
Data outputs
DESCRIPTION
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
PIN CONFIGURATION
E
Q0
1
2
20 V
CC
19 Q7
18 D7
LOGIC SYMBOL
3
4
7
8
13
14
17
18
D0 3
D1 4
Q1
Q2
5
6
D0
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
V
CC
= Pin 20
GND = Pin 10
2
Q0
11
1
D2 7
D3 8
Q3
9
CP
E
D1
D2
D3
D4
D5
D6
D7
Q1
Q2
Q3
Q4
Q5
Q6
Q7
5
6
9
12
15
16
19
GND 10
SF00350
SF00351
1996 Mar 12
2
853–0026 16555
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
LOGIC SYMBOL (IEEE/IEC)
1
11
G1
FUNCTION TABLE
INPUTS
E
CP
↑
↑
Dn
h
l
OUTPUTS
Qn
H
L
Load “1”
Load “0”
OPERATING MODE
1C2
l
3
4
7
8
13
14
17
18
2D
2
5
6
9
12
15
16
19
l
h
↑
X
no change
Hold (do nothing)
H
X
X
no change
H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High
clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High
clock transition
X = Don’t care
↑
= Low-to-High clock transition
SF00352
LOGIC DIAGRAM
D0
3
1
E
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
18
D7
D
CP
11
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
D
CP
Q
CP
2
Q0
V
CC
= Pin 20
GND = Pin 10
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SF00353
1996 Mar 12
3
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free air temperature range.)
SYMBOL
V
CC
V
IN
I
IN
V
OUT
I
OUT
T
amb
T
stg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free air temperature range
Storage temperature range
PARAMETER
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to V
CC
40
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°
C
°C
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V
CC
V
IH
V
IL
I
Ik
I
OH
I
OL
T
amb
Supply voltage
High–level input voltage
Low–level input voltage
Input clamp current
High–level output current
Low–level output current
Operating free air temperature range
0
4.5
2.0
0.8
–18
–1
20
+70
LIMITS
NOM
5.0
MAX
5.5
V
V
V
mA
mA
mA
UNIT
°
C
DC ELECTRICAL CHARACTERISTICS
(Over recommended operating free-air temperature range unless otherwise noted.)
SYMBOL
PARAMETER
TEST
CONDITIONS
1
E & CP inputs
V
OH
High-level output voltage
Other inputs
V
CC
= MIN, V
IL
= 0.0V
3
,
V
IH
= 4.5V
3
, I
OH
= MAX
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OH
= MAX
V
OL
V
IK
I
I
I
IH
I
IL
I
OS
I
CC
Low-level output voltage
V
CC
= MIN, V
IL
= MAX,
V
IH
= MIN, I
OL
= MAX
Input clamp voltage
Input current at maximum input voltage
High–level input current
Low–level input current
Short circuit output current
4
Supply current (total)
I
CCH
I
CCL
V
CC
= MIN, I
I
= I
IK
V
CC
= 0.0V, V
I
= 7.0V
V
CC
= MAX, V
I
= 2.7V
V
CC
= MAX, V
I
= 0.5V
V
CC
= MAX
V
CC
= MAX
V
CC
= MAX
–60
27
29
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
±10%V
CC
±5%V
CC
MIN
2.5
2.7
2.5
2.7
0.35
0.35
–0.73
0.50
0.50
-1.2
100
20
–20
–150
40
43
3.4
LIMITS
TYP
2
MAX
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
UNIT
Notes to DC electrical characteristics
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type.
2. All typical values are at V
CC
= 5V, T
amb
= 25
°
C.
3. To reduce the effect of external noise during test. Special test conditions are not necessary for the ’377A.
4. Not more than one output should be shorted at a time. For testing I
OS
, the use of high-speed test apparatus and/or sample-and-hold
techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting
of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any
sequence of parameter tests, I
OS
tests should be performed last.
1996 Mar 12
4
Philips Semiconductors
Product specification
Octal D-type flip-flop with enable
74F377A
AC CHARACTERISTICS
LIMITS
T
amb
= +25
o
C
V
CC
= +5.0V
C
L
= 50pF
R
L
= 500Ω
MIN
f
MAX
t
PLH
t
PHL
Maximum clock frequency
Propagation delay
CP to Qn
1
1
150
3.0
4.5
TYP
165
5.0
6.5
8.0
9.0
MAX
T
amb
=0
o
C to +70
o
C
V
CC
= +5.0V
±10%
C
L
= 50pF
R
L
= 500Ω
MIN
120
2.5
4.0
9.0
10.5
MAX
MHz
ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
AC SETUP REQUIREMENTS
LIMITS
T
amb
= +25
o
C
V
CC
= +5.0V
C
L
= 50pF
R
L
= 500Ω
MIN
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
s
(H)
t
s
(L)
t
h
(H)
t
h
(L)
t
w
(H)
t
w
(L)
Setup time, High or Low
Dn to CP
Hold time, High or Low
Dn to CP
Setup time, High or Low
E to CP
Hold time, High or Low
E to CP
Clock Pulse width
High or Low
2
2
2
2
1
2.5
2.5
1.0
0.0
3.0
4.0
0.0
0.0
4.0
4.0
TYP
MAX
T
amb
= 0
o
C to +70
o
C
V
CC
= +5.0V
±10%
C
L
= 50pF
R
L
= 500Ω
MIN
2.5
2.5
1.0
0.0
3.0
4.5
0.0
0.0
5.0
4.0
MAX
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
WAVEFORM
UNIT
AC WAVEFORMS
1/f
max
D
n
CP
V
M
t
w
(H)
t
PHL
V
M
t
w
(L)
t
PLH
V
M
t
s
V
M
V
M
t
h
V
M
V
M
Qn
E
V
M
V
M
t
h
= 0
V
M
V
M
t
h
= 0
SF00294
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width and Maximum Clock Frequency
CP
NOTE:
For all waveforms, V
M
= 1.5V.
The shaded areas indicate when the input is permitted to change for predictable output
performance.
t
s
(L)
V
M
t
s
(H)
V
M
SF01237
Waveform 2. Data and Enable
Setup and Hold Times
1996 Mar 12
5
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