DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
The SN54 / 74LS90, SN54 / 74LS92 and SN54 / 74LS93 are high-speed
4-bit ripple type counters partitioned into two sections. Each counter has a di-
vide-by-two section and either a divide-by-five (LS90), divide-by-six (LS92) or
divide-by-eight (LS93) section which are triggered by a HIGH-to-LOW transi-
tion on the clock inputs. Each section can be used separately or tied together
(Q to CP) to form BCD, bi-quinary, modulo-12, or modulo-16 counters. All of
the counters have a 2-input gated Master Reset (Clear), and the LS90 also
has a 2-input gated Master Set (Preset 9).
SN54/74LS90
SN54/74LS92
SN54/74LS93
DECADE COUNTER;
DIVIDE-BY-TWELVE COUNTER;
4-BIT BINARY COUNTER
LOW POWER SCHOTTKY
•
Low Power Consumption . . . Typically 45 mW
•
High Count Rates . . . Typically 42 MHz
•
Choice of Counting Modes . . . BCD, Bi-Quinary, Divide-by-Twelve,
Binary
•
Input Clamp Diodes Limit High Speed Termination Effects
PIN NAMES
LOADING
(Note a)
HIGH
CP0
CP1
CP1
MR1, MR2
MS1, MS2
Q0
Q1, Q2, Q3
Clock (Active LOW going edge) Input to
÷2
Section
Clock (Active LOW going edge) Input to
÷5
Section (LS90),
÷6
Section (LS92)
Clock (Active LOW going edge) Input to
÷8
Section (LS93)
Master Reset (Clear) Inputs
Master Set (Preset-9, LS90) Inputs
Output from
÷2
Section (Notes b & c)
Outputs from
÷5
(LS90),
÷6
(LS92),
÷8
(LS93) Sections (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
LOW
1.5 U.L.
14
14
1
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
1
2.0 U.L.
1.0 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
5 (2.5) U.L.
14
1
D SUFFIX
SOIC
CASE 751A-02
ORDERING INFORMATION
SN54LSXXJ
SN74LSXXN
SN74LSXXD
Ceramic
Plastic
SOIC
NOTES:
a. 1 TTL Unit Load (U.L.) = 40
µA
HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military, (54) and 5 U.L. for commercial (74)
b.
Temperature Ranges.
c. The Q0 Outputs are guaranteed to drive the full fan-out plus the CP1 input of the device.
d. To insure proper operation the rise (tr) and fall time (tf) of the clock must be less than 100 ns.
LOGIC SYMBOL
LS90
6 7
1 2
MS
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PINS 4, 13
14
1
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
6 7 12 11 9 8
VCC = PIN 5
GND = PIN 10
NC = PINS 2, 3, 4, 13
14
1
CP0
CP1
MR Q0 Q1 Q2 Q3
1 2
2 3 12 9 8 11
VCC = PIN 5
GND = PIN 10
NC = PIN 4, 6, 7, 13
LS92
LS93
14
1
FAST AND LS TTL DATA
5-90
SN54/74LS90
•
SN54/74LS92
•
SN54/74LS93
LOGIC DIAGRAM
LS90
MS1
MS2
6
7
CONNECTION DIAGRAM
DIP
(TOP VIEW)
CP1 1
14 CP0
13 NC
12 Q0
11 Q3
10 GND
9 Q1
8 Q2
14
S
J DQ
CP
KC Q
D
S
J DQ
CP
KC Q
D
S
J DQ
CP
KC Q
D
S
R DQ
CP
SC Q
D
MR1 2
MR2 3
NC 4
VCC 5
MS1 6
CP0
1
CP1
MR1
MR2
2
12
3
9
8
11
MS2 7
Q3
Q0
Q1
Q2
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
LOGIC DIAGRAM
LS92
CONNECTION DIAGRAM
DIP
(TOP VIEW)
CP1 1
14 CP0
13 NC
12 Q0
11 Q1
10 GND
9 Q2
8 Q3
CP0
14
J
Q
J
Q
J
Q
J
Q
NC 2
NC 3
NC 4
VCC 5
MR1 6
CP
KC Q
D
1
CP
KC Q
D
CP
KC Q
D
CP
KC Q
D
CP1
6
MR1
MR2
12
7
11
9
8
MR2 7
Q3
Q0
Q1
Q2
NC = NO INTERNAL CONNECTION
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
LOGIC DIAGRAM
LS93
CONNECTION DIAGRAM
DIP
(TOP VIEW)
CP1 1
14 CP0
13 NC
12 Q0
11 Q3
10 GND
9 Q1
8 Q2
CP0
14
J
CP
Q
J
CP
Q
J
CP
Q
J
CP
Q
MR1 2
MR2 3
NC 4
VCC 5
NC 6
KC Q
D
1
KC Q
D
KC Q
D
KC Q
D
CP1
MR1
MR2
2
12
3
9
8
11
Q0
Q1
Q2
Q3
= PIN NUMBERS
VCC = PIN 5
GND = PIN 10
NC 7
NC = NO INTERNAL CONNECTION
NOTE:
The Flatpak version has the same
pinouts (Connection Diagram) as
the Dual In-Line Package.
FAST AND LS TTL DATA
5-91
SN54/74LS90
•
SN54/74LS92
•
SN54/74LS93
FUNCTIONAL DESCRIPTION
The LS90, LS92, and LS93 are 4-bit ripple type Decade,
Divide-By-Twelve, and Binary Counters respectively. Each
device consists of four master/slave flip-flops which are
internally connected to provide a divide-by-two section and a
divide-by-five (LS90), divide-by-six (LS92), or divide-by-eight
(LS93) section. Each section has a separate clock input which
initiates state changes of the counter on the HIGH-to-LOW
clock transition. State changes of the Q outputs do not occur
simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and
should not be used for clocks or strobes. The Q0 output of
each device is designed and specified to drive the rated
fan-out plus the CP1 input of the device.
A gated AND asynchronous Master Reset (MR1
•
MR2) is
provided on all counters which overrides and clocks and
resets (clears) all the flip-flops. A gated AND asynchronous
Master Set (MS1
•
MS2) is provided on the LS90 which
overrides the clocks and the MR inputs and sets the outputs to
nine (HLLH).
Since the output from the divide-by-two section is not
internally connected to the succeeding stages, the devices
may be operated in various counting modes.
LS90
A. BCD Decade (8421) Counter — The CP1 input must be ex-
ternally connected to the Q0 output. The CP0 input receives
the incoming count and a BCD count sequence is pro-
duced.
B. Symmetrical Bi-quinary Divide-By-Ten Counter — The Q3
output must be externally connected to the CP0 input. The
input count is then applied to the CP1 input and a divide-by-
ten square wave is obtained at output Q0.
C. Divide-By-Two and Divide-By-Five Counter — No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function (CP 0 as the
input and Q0 as the output). The CP1 input is used to obtain
binary divide-by-five operation at the Q3 output.
LS92
A. Modulo 12, Divide-By-Twelve Counter — The CP1 input
must be externally connected to the Q0 output. The CP0 in-
put receives the incoming count and Q3 produces a sym-
metrical divide-by-twelve square wave output.
B. Divide-By-Two and Divide-By-Six Counter —No external
interconnections are required. The first flip-flop is used as a
binary element for the divide-by-two function. The CP1 in-
put is used to obtain divide-by-three operation at the Q1
and Q2 outputs and divide-by-six operation at the Q3 out-
put.
LS93
A. 4-Bit Ripple Counter — The output Q0 must be externally
connected to input CP1. The input count pulses are applied
to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are
performed at the Q0, Q1, Q2, and Q3 outputs as shown in
the truth table.
B. 3-Bit Ripple Counter— The input count pulses are applied
to input CP1. Simultaneous frequency divisions of 2, 4, and
8 are available at the Q1, Q2, and Q3 outputs. Independent
use of the first flip-flop is available if the reset function coin-
cides with reset of the 3-bit ripple-through counter.
FAST AND LS TTL DATA
5-92
SN54/74LS90
•
SN54/74LS92
•
SN54/74LS93
GUARANTEED OPERATING RANGES
Symbol
VCC
TA
IOH
IOL
Supply Voltage
Operating Ambient Temperature Range
Output Current — High
Output Current — Low
Parameter
54
74
54
74
54, 74
54
74
Min
4.5
4.75
– 55
0
Typ
5.0
5.0
25
25
Max
5.5
5.25
125
70
– 0.4
4.0
8.0
Unit
V
°C
mA
mA
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE
(unless otherwise specified)
Limits
Symbol
VIH
VIL
VIK
VOH
Parameter
Input HIGH Voltage
54
Input LOW Voltage
74
Input Clamp Diode Voltage
54
Output HIGH Voltage
74
54, 74
VOL
Output LOW Voltage
74
Input HIGH Current
0.1
Input LOW Current
MS, MR
CP0
CP1 (LS90, LS92)
CP1 (LS93)
Short Circuit Current (Note 1)
Power Supply Current
– 20
– 0.4
– 2.4
– 3.2
– 1.6
–100
15
0.35
0.5
20
IIH
V
µA
mA
2.7
3.5
0.25
0.4
V
V
2.5
– 0.65
3.5
0.8
– 1.5
V
V
Min
2.0
0.7
V
Typ
Max
Unit
V
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
Guaranteed Input LOW Voltage for
All Inputs
VCC = MIN, IIN = – 18 mA
VCC = MIN, IOH = MAX, VIN = VIH
or VIL per Truth Table
IOL = 4.0 mA
IOL = 8.0 mA
VCC = VCC MIN,
VIN = VIL or VIH
per Truth Table
VCC = MAX, VIN = 2.7 V
VCC = MAX, VIN = 7.0 V
IIL
mA
VCC = MAX, VIN = 0.4 V
IOS
ICC
mA
mA
VCC = MAX
VCC = MAX
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.
FAST AND LS TTL DATA
5-94
DSP and ARM Processors
京公网安备 11010802033920号
EEWORLD
