®
74LVQ02
QUAD 2-INPUT NOR GATE
s
s
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 5 ns (TYP.) at V
CC
= 3.3V
COMPATIBLE WITH TTL OUTPUTS
LOW POWER DISSIPATION:
I
CC
= 2
µA
(MAX.) at T
A
= 25
o
C
LOW NOISE:
V
OLP
= 0.3 V (TYP.) at V
CC
= 3.3V
75
Ω
TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12 mA (MIN)
PCI BUS LEVELS GUARANTEED AT 24mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2V to 3.6V (1.2V Data Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 02
IMPROVED LATCH-UP IMMUNITY
M
(Micro Package)
T
(TSSOP Package)
ORDER CODES :
74LVQ02M
74LVQ02T
technology. It is ideal for low power and low noise
3.3V applications.
The internal circuit is composed of 3 stages
including buffer output, which enables high noise
immunity and stable output.
It has better speed performance at 3.3V than 5V
LS-TTL family combined with the true CMOS low
power consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
DESCRIPTION
The LVQ02 is a low voltage CMOS QUAD
2-INPUT NOR GATE fabricated with sub-micron
silicon gate and double-layer metal wiring C
2
MOS
PIN CONNECTION AND IEC LOGIC SYMBOLS
February 1999
1/8
74LVQ02
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
2, 5, 8, 11
3, 6, 9, 12
1, 4, 10, 13
7
14
SYMBOL
1A to 4A
1B to 4B
1Y to 4Y
GND
V
CC
NAME AND FUNCT ION
Data Inputs
Data Inputs
Data Outputs
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
A
L
L
H
H
B
L
H
L
H
Y
H
L
L
L
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7
-0.5 to V
CC
+ 0.5
-0.5 to V
CC
+ 0.5
±
20
±
20
±
50
±
200
-65 to +150
300
Unit
V
V
V
mA
mA
mA
mA
o
o
I
CC
or I
GND
DC V
CC
or Ground Current
C
C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
T
op
dt/dv
Input Voltage
Output Voltage
Operating Temperature:
Input Rise and Fall Time (V
CC
= 3V) (note 2)
Parameter
Supply Voltage (note 1)
Valu e
2 to 3.6
0 to V
CC
0 to V
CC
-40 to +85
0 to 10
Unit
V
V
V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V
2) V
IN
from 0.8V to 2V
2/8
74LVQ02
DC SPECIFICATIONS
Symb ol
Parameter
V
CC
(V)
V
IH
V
IL
V
OH
High Level Input Voltage
Low Level Input Voltage
High Level Output
Voltage
Low Level Output
Voltage
Input Leakage Current
Quiescent Supply
Current
Dynamic Output Current
(note 1, 2)
3.0 to
3.6
3.0
V
I (* )
=
V
IL
V
I
=
V
IH
or
V
IL
(*)
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
2.0
0.8
T yp.
Max.
-40 to 85 C
Min.
2.0
0.8
2.9
2.48
2.2
0.002
0
0.1
0.36
±
0.1
2
36
-25
0.1
0.44
0.55
±
1
20
2.99
Max.
o
Un it
V
V
V
I
O
=-50
µA
I
O
=-12 mA
I
O
=-24 mA
I
O
=50
µA
I
O
=12 mA
I
O
=24 mA
2.9
2.58
V
OL
3.0
V
µ
A
µA
mA
mA
I
I
I
CC
I
OLD
I
OHD
3.6
3.6
3.6
V
I
= V
CC
or GND
V
I
= V
CC
or GND
V
OLD
= 0.8 V max
V
OHD
= 2 V min
1) Maximum test duration 2ms, one output loaded attime
2) Incident wave switching is guaranteed on transmission lines with impedances as low as 50
Ω.
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
V
OLP
V
OLV
V
IHD
V
ILD
Dynamic Low Voltage
Quiet Output (note 1, 2)
Dynamic High Voltage
Input (note 1, 3)
Dynamic Low Voltage
Input (note 1, 3)
3.3
-0.8
3.3
3.3
C
L
= 50 pF
0.8
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
0.3
-0.3
2
Max.
0.8
-40 to 85 C
Min.
Max.
o
Un it
V
1) Worst case package.
2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (V
ILD
), 0V to threshold (V
IHD
).,f=1MHz.
3/8
74LVQ02
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, R
L
= 500
Ω,
Input t
r
= t
f
=3 ns)
Symb ol
Parameter
V
CC
(V)
t
PLH
t
PHL
t
OSLH
t
OSHL
Propagation Delay Time
Output to Output Skew
Time (note 1, 2)
2.7
3.3
(*)
2.7
3.3
(*)
T est Con ditio n
o
Valu e
-40 to 85 C
T
A
= 25 C
Min. T yp. Max. Min. Max.
6.0
5.0
0.5
0.5
10.5
7.5
1.5
1.5
12.0
8.0
1.5
1.5
o
Un it
ns
ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the
same direction, either HIGH or LOW (t
OSLH
= |t
PLHm
- t
PLHn
|, t
OSHL
= |t
PHLm
- t
pHLn
|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V
±
0.3V
CAPACITIVE CHARACTERISTICS
Symb ol
Parameter
V
CC
(V)
C
IN
C
PD
Input Capacitance
Power Dissipation
Capacitance (note 1)
3.3
3.3
f
IN
= 10 MHz
Test Co nditions
o
Valu e
T
A
= 25 C
Min.
T yp.
4
40
Max.
-40 to 85 C
Min.
Max.
o
Un it
pF
pF
1) C
PD
isdefined as the value of the IC’sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto
Test Circuit).Average operting current can be obtained by the following equation. I
CC
(opr) = C
PD
•
V
CC
•f
IN
+ I
CC
/4(per gate)
4/8
74LVQ02
TEST CIRCUIT
C
L
= 50 pF or equivalent (includes jigand probe capacitance)
R
L
= R
1
= 500
Ω
orequivalent
R
T
= Z
OUT
of pulse generator (typically 50Ω)
WAVEFORM: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
5/8
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