74LVQ02T datasheet, PDF - EEWORLD Datasheet

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74LVQ02T: DescriptionQUAD 2-INPUT NOR GATE; Categorylogic logic; File Size53KB，8 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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74LVQ02T Overview

QUAD 2-INPUT NOR GATE

74LVQ02T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	STMicroelectronics
Parts packaging code	TSSOP
package instruction	TSSOP-14
Contacts	14
Reach Compliance Code	_compli
Is Samacsys	N
series	LVQ
JESD-30 code	R-PDSO-G14
JESD-609 code	e0
length	5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NOR GATE
MaximumI(ol)	0.024 A
Number of functions	4
Number of entries	2
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP14,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Prop。Delay @ Nom-Su	8 ns
propagation delay (tpd)	13.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.2 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2 V
Nominal supply voltage (Vsup)	2.7 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	4.4 mm
Base Number Matches	1

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74LVQ02

QUAD 2-INPUT NOR GATE

HIGH SPEED: t

= 5 ns (TYP.) at V

= 3.3V

COMPATIBLE WITH TTL OUTPUTS

LOW POWER DISSIPATION:

= 2

µA

(MAX.) at T

= 25

LOW NOISE:

OLP

= 0.3 V (TYP.) at V

= 3.3V

Ω

TRANSMISSION LINE DRIVING

CAPABILITY

SYMMETRICAL OUTPUT IMPEDANCE:

| = I

= 12 mA (MIN)

PCI BUS LEVELS GUARANTEED AT 24mA

BALANCED PROPAGATION DELAYS:

PLH

≅

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 02

IMPROVED LATCH-UP IMMUNITY

(Micro Package)

(TSSOP Package)

ORDER CODES :

74LVQ02M

74LVQ02T

technology. It is ideal for low power and low noise

3.3V applications.

The internal circuit is composed of 3 stages

including buffer output, which enables high noise

immunity and stable output.

It has better speed performance at 3.3V than 5V

LS-TTL family combined with the true CMOS low

power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The LVQ02 is a low voltage CMOS QUAD

2-INPUT NOR GATE fabricated with sub-micron

silicon gate and double-layer metal wiring C

MOS

PIN CONNECTION AND IEC LOGIC SYMBOLS

February 1999

1/8

74LVQ02T Related Products

	74LVQ02T	74LVQ02M
Description	QUAD 2-INPUT NOR GATE	QUAD 2-INPUT NOR GATE
Is it Rohs certified?	incompatible	incompatible
Maker	STMicroelectronics	STMicroelectronics
Parts packaging code	TSSOP	SOIC
package instruction	TSSOP-14	SOP, SOP14,.25
Contacts	14	14
Reach Compliance Code	_compli	_compli
series	LVQ	LVQ
JESD-30 code	R-PDSO-G14	R-PDSO-G14
JESD-609 code	e0	e0
length	5 mm	8.65 mm
Load capacitance (CL)	50 pF	50 pF
Logic integrated circuit type	NOR GATE	NOR GATE
MaximumI(ol)	0.024 A	0.024 A
Number of functions	4	4
Number of entries	2	2
Number of terminals	14	14
Maximum operating temperature	125 °C	125 °C
Minimum operating temperature	-55 °C	-55 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	SOP
Encapsulate equivalent code	TSSOP14,.25	SOP14,.25
Package shape	RECTANGULAR	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED
power supply	3.3 V	3.3 V
Prop。Delay @ Nom-Su	8 ns	9.5 ns
propagation delay (tpd)	13.5 ns	13.5 ns
Certification status	Not Qualified	Not Qualified
Schmitt trigger	NO	NO
Maximum seat height	1.2 mm	1.75 mm
Maximum supply voltage (Vsup)	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2 V	2 V
Nominal supply voltage (Vsup)	2.7 V	2.7 V
surface mount	YES	YES
technology	CMOS	CMOS
Temperature level	MILITARY	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	GULL WING	GULL WING
Terminal pitch	0.65 mm	1.27 mm
Terminal location	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED
width	4.4 mm	3.9 mm

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