74LVT32373GX datasheet, PDF - EEWORLD Datasheet

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74LVT32373GX: DescriptionLow Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary); Categorylogic logic; File Size159KB，6 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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74LVT32373GX Overview

Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)

74LVT32373GX Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Fairchild
Parts packaging code	BGA
package instruction	LFBGA, BGA96,6X16,32
Contacts	96
Reach Compliance Code	compli
series	LVT
JESD-30 code	R-PBGA-B96
JESD-609 code	e0
length	13.5 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	BUS DRIVER
MaximumI(ol)	0.064 A
Humidity sensitivity level	3
Number of digits	8
Number of functions	4
Number of ports	2
Number of terminals	96
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	3-STATE
Output polarity	TRUE
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA96,6X16,32
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
method of packing	TR
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
propagation delay (tpd)	4.8 ns
Certification status	Not Qualified
Maximum seat height	1.4 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	BICMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	5.5 mm

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Preliminary

74LVT32373 • 74LVTH32373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)

August 2001

Revised August 2001

74LVT32373 • 74LVTH32373

Low Voltage 32-Bit Transparent Latch

with 3-STATE Outputs (Preliminary)

General Description

The LVT32373 and LVTH32373 contain thirty-two non-

inverting latches with 3-STATE outputs and are intended

for bus oriented applications. The device is byte controlled.

The flip-flops appear transparent to the data when the

Latch Enable (LE) is HIGH. When LE is LOW, the data that

meets the setup time is latched. Data appears on the bus

when the Output Enable (OE) is LOW. When OE is HIGH,

the outputs are in a high impedance state.

The LVTH32373 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These latches are designed for low-voltage (3.3V) V

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVT32373 and LVTH32373

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH32373),

also available without bushold feature (74LVT32373)

Live insertion/extraction permitted

Power Up/Down high impedance provides glitch-free

bus loading

Outputs source/sink

−

32 mA/

64 mA

ESD performance:

Human-body model

2000V

Machine model

200V

Charged-device model

1000V

Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

(Preliminary)

Ordering Code:

Order Number

74LVT32373GX

(Note 1)

74LVTH32373GX

(Note 1)

Package Number

BGA96A

(Preliminary)

BGA96A

(Preliminary)

Package Description

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

Note 1:

BGA package available in Tape and Reel only.

Logic Symbol

DS500548

www.fairchildsemi.com

74LVT32373GX Related Products

	74LVT32373GX	74LVT32373	74LVTH32373GX	74LVTH32373
Description	Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)	Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)	Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)	Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary)

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