INTEGRATED CIRCUITS
74LVT74
3.3V Dual D-type flip-flop
Product specification
IC24 Data Handbook
1996 Aug 28
Philips
Semiconductors
Philips Semiconductors
Product specification
3.3V Dual D-type flip-flop
74LVT74
QUICK REFERENCE DATA
SYMBOL
PARAMETER
Propagation
delay
CPn to Qn
Input
capacitance
Total supply
current
CONDITIONS
T
amb
= 25°C;
GND = 0V
C
L
= 50pF;
V
CC
= 3.3V
V
I
= 0V or 3.0V
V
CC
= 3.6V
TYPICAL
UNIT
DESCRIPTION
The 74LVT74 is a dual positive edge-triggered D-type flip-flop
featuring individual data, clock, set, and reset inputs; also true and
complementary outputs. Set (SD) and reset (RD) are asynchronous
active low inputs and operate independently of the clock input.
When set and reset are inactive (high), data at the D input is
transferred to the Q and Q outputs on the low-to-high transition of
the clock. Data must be stable just one setup time prior to the
low-to-high transition of the clock for predictable operation. Clock
triggering occurs at a voltage level and is not directly related to the
transition time of the positive-going pulse. Following the hold time
interval, data at the D input may be changed without affecting the
levels of the output.
t
PLH
t
PHL
C
IN
I
CC
3.1
3.6
3
0.5
ns
pF
mA
PIN CONFIGURATION
RD0
D0
CP0
SD0
Q0
Q0
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
RD1
D1
CP1
SD1
Q1
Q1
PIN DESCRIPTION
PIN NUMBER
2, 12
3, 11
4, 10
1, 13
5, 6, 8, 9
SF00045
SYMBOL
D0, D1
CP0, CP1
SD0, SD1
RD0, RD1
Qn, Qn
NAME AND FUNCTION
Data inputs
Clock inputs (active rising edge)
Set inputs (active LOW)
Reset inputs (active LOW)
Data outputs
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
2
12
4
3
D0 D1
3
4
1
11
10
13
CP0
1
SD0
RD0
10
CP1
SD1
RD1
Q0 Q0 Q1 Q1
V
CC
= Pin 14
GND = Pin 7
11
C2
12
13
2D
R
8
S
9
C1
2
1D
R
6
S
&
5
5
6
9
8
SA00359
SF00047
ORDERING INFORMATION
PACKAGES
14-Pin Plastic SO
14-Pin Plastic SSOP
14-Pin Plastic TSSOP
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74LVT74 D
74LVT74 DB
74LVT74 PW
NORTH AMERICA
74LVT74 D
74LVT74 DB
74LVT74PW DH
DWG NUMBER
SOT108-1
SOT337-1
SOT402-1
1996 Aug 28
2
853-1872 17244
Philips Semiconductors
Product specification
3.3V Dual D-type flip-flop
74LVT74
LOGIC DIAGRAM
FUNCTION TABLE
INPUTS
OUTPUTS
D
X
X
X
h
l
X
Q
H
L
H
H
L
NC
Q
L
H
H
L
H
NC
SD
L
RD
H
L
L
H
H
H
CP
X
X
X
↑
↑
↑
OPERATING
MODE
Asynchronous set
Asynchronous reset
Undetermined*
Load “1”
Load “0”
Hold
SD
4, 10
RD
1, 13
5, 9
Q
H
L
H
CP
3, 11
6, 8
Q
H
H
D
2, 12
V
CC
= Pin 14
GND = Pin 7
SF00048
NOTES:
H = High voltage level
h = High voltage level one setup time prior to low-to-high
clock transition
L = Low voltage level
l = Low voltage level one setup time prior to low-to-high
clock transition
NC= No change from the previous setup
X = Don’t care
↑
= Low-to-high clock transition
↑
= Not low-to-high clock transition
* = This setup is unstable and will change when either set
or reset return to the high level.
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input
voltage
3
V
O
< 0
Output in Off or High state
Output in High state
Output in Low state
DC output diode current
DC output voltage
3
DC output current
out ut
Storage temperature range
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
–32
64
–65 to 150
UNIT
V
mA
V
mA
V
mA
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Low-level Input voltage
High-level output current
Low-level output current
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
LIMITS
MIN
2.7
0
2.0
0.8
–20
32
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
1996 Aug 28
3
Philips Semiconductors
Product specification
3.3V Dual D-type flip-flop
74LVT74
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions
Voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
V
IK
V
OH
PARAMETER
Input clamp voltage
High-level output voltage
TEST CONDITIONS
V
CC
= 2.7V; I
IK
= –18mA
V
CC
= 2.7 to 3.6V; I
OH
= –100µA
V
CC
= 2.7V; I
OH
= –6mA
V
CC
= 3.0V; I
OH
= –20mA
V
CC
= 2.7V; I
OL
= 100µA
V
OL
Low-level output voltage
V
CC
= 2.7V; I
OL
= 24mA
V
CC
= 3.0V; I
OL
= 32mA
I
I
I
OFF
I
CC
∆I
CC
C
I
In ut
Input leakage current
Output off current
Quiescent supply current
Additional supply current per input pin
2
Input capacitance
V
CC
= 0 or 3.6V; V
I
= 5.5V
V
CC
= 3.6V; V
I
= V
CC
or GND
V
CC
= 0V; V
I
or V
O
= 0 to 4.5V
V
CC
= 3.6V; Outputs High, V
I
= GND or
V
CC,
I
O =
0
V
CC
= 3V to 3.6V; One input at V
CC
–0.6V,
Other inputs at V
CC
or GND
V
I
= 3V or 0
3
0.5
V
CC
–0.2
2.4
2.0
0.2
0.5
0.5
10
±1
±100
1
0.2
µA
µA
mA
µA
pF
V
V
Temp = -40°C to +85°C
MIN
TYP
1
MAX
–1.2
V
UNIT
NOTES:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
2. This is the increase in supply current for each input at the specificed voltage level other than V
CC
or GND.
AC CHARACTERISTICS
GND = 0V; t
R
= t
F
= 2.5ns; C
L
= 50pF, R
L
= 500Ω; T
amb
= –40°C to +85°C.
LIMITS
SYMBOL
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
PARAMETER
Maximum clock frequency
Propagation delay
CPn to Qn or Qn
Propagation delay
SDn, RDn to Qn or Qn
WAVEFORM
MIN
1
1
2
150
1.0
1.0
1.0
1.0
V
CC
= 3.3V
±
0.3V
TYP
1
345
3.1
3.6
3.1
3.0
4.8
5.0
5.0
4.4
5.8
5.0
6.2
4.8
MAX
V
CC
= 2.7V
MAX
MHz
ns
ns
UNIT
NOTE:
1. All typical values are at V
CC
= 3.3V and T
amb
= 25°C.
AC SETUP REQUIREMENTS
LIMITS
SYMBOL
t
S
(H)
t
S
(L)
t
h
(H)
t
h
(L)
t
W
(H)
t
W
(L)
t
W
(L)
t
rec
Setup time
Dn to CPn
Holdtime
Dn to CPn
CPn Pulse Width
SDn, RDn Pulse Width
Recovery time
SDn, RDn tp CPn
PARAMETER
WAVEFORM
V
CC
= 3.3V
±
0.3V
MIN
1
1
1
2
3
1.7
1.4
0.3
0
2.0
2.0
2.0
0.5
TYP
0.6
0.4
–0.3
–0.6
1.0
1.2
1.0
–0.3
V
CC
= 2.7V
MIN
1.8
1.6
0.3
0
3.0
3.0
3.0
0.5
ns
ns
UNIT
ns
1996 Aug 28
4
Philips Semiconductors
Product specification
3.3V Dual D-type flip-flop
74LVT74
AC WAVEFORMS
V
M
= 1.5V, V
IN
= GND to 2.7V
t
w
(L)
V
M
Dn
V
M
t
su
(L)
V
M
t
h
(L)
1/f
max
V
M
t
su
(H)
V
M
t
h
(H)
SDn V
M
CPn
V
M
t
w
(H)
t
PLH
V
M
t
w
(L)
RDn
V
M
t
PLH
t
PHL
Qn
V
M
t
PHL
t
w
(L)
V
M
t
PHL
V
M
Qn
V
M
t
PLH
V
M
t
PHL
V
M
t
PLH
Qn
V
M
V
M
Qn
V
M
V
M
SF00050
SF00049
Waveform 1. Propagation delay for data to output,
data setup time and hold times, and clock width,
and maximum clock frequency
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
SDn or RDn
V
M
t
rec
CPn
V
M
SF00051
Waveform 3. Recovery time for set or reset to clock
TEST CIRCUIT AND WAVEFORMS
V
CC
90%
NEGATIVE
PULSE
V
IN
PULSE
GENERATOR
R
T
D.U.T.
C
L
R
L
POSITIVE
PULSE
V
OUT
V
M
10%
t
THL
(t
F
)
t
TLH
(t
R
)
90%
V
M
t
W
90%
V
M
10%
0V
10%
0V
t
TLH
(t
R
)
t
THL
(t
F
)
AMP (V)
t
W
V
M
90%
AMP (V)
Test Circuit for Outputs
10%
V
M
= 1.5V
Input Pulse Definition
DEFINITIONS
R
L
= Load resistor; see AC CHARACTERISTICS for value.
C
L
= Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
R
T
= Termination resistance should be equal to Z
OUT
of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY
Amplitude
74LVT
2.7V
Rep. Rate
≤10MHz
t
W
t
R
t
F
500ns
≤2.5ns ≤2.5ns
SV00022
1996 Aug 28
5
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