74LVT2245 • 74LVTH2245 Low Voltage Octal Bidirectional Transceiver with 3-STATE Inputs/Outputs and 25:
Series Resistors in the B Port Outputs
November 1999
Revised March 2005
74LVT2245 • 74LVTH2245
Low Voltage Octal Bidirectional Transceiver with
3-STATE Inputs/Outputs and 25: Series Resistors
in the B Port Outputs
General Description
The LVT2245 and LVTH2245 contain eight non-inverting
bidirectional buffers with 3-STATE outputs and are
intended for bus-oriented applications. The Transmit/
Receive (T/R) input determines the direction of data flow
through the bidirectional transceiver. Transmit (active-
HIGH) enables data from A Ports to B Ports; Receive
(active-LOW) enables data from B Ports to A Ports. The
Output Enable input, when HIGH, disables both A and B
Ports by placing them in a high impedance state. The
equivalent 25
:
-series resistor in the B Port helps reduce
output overshoot and undershoot.
The LVTH2245 data inputs include bushold, eliminating the
need for external pull-up resistors to hold unused inputs.
These transceivers are designed for low voltage (3.3V)
V
CC
applications, but with the capability to provide a TTL
interface to a 5V environment. The LVT2245 and
LVTH2245 are fabricated with an advanced BiCMOS tech-
nology to achieve high speed operation similar to 5V ABT
while maintaining low power dissipation.
Features
s
Input and output interface capability to systems at
5V V
CC
s
Equivalent 25
:
series resistor on B Port outputs
s
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH2245),
also available without bushold feature (74LVT2245)
s
Live insertion/extraction permitted
s
Power Up/Down high impedance provides glitch-free
bus loading
s
Outputs source/sink
12 mA/
12 mA on B Port,
32 mA/
64 mA on A Port
s
Latch-up performance exceeds 500 mA
s
ESD performance:
Human-body model
!
2000V
Machine model
!
200V
Charged-device model
!
1000V
Ordering Code:
Order Number
74LVT2245WM
74LVT2245SJ
74LVT2245MSA
74LVT2245MTC
74LVT2245MTCX_NL
(Note 1)
74LVTH2245WM
74LVTH2245SJ
74LVTH2245MSA
74LVTH2245MTC
74LVTH2245MTCX_NL
(Note 1)
Package
Number
M20B
M20D
MSA20
MTC20
MTC20
M20B
M20D
MSA20
MTC20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
“_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS012173
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74LVT2245 • 74LVTH2245
DC Electrical Characteristics
Symbol
V
IK
V
IH
V
IL
V
OH
Parameter
Input Clamp Diode Voltage
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
A Port
B Port
V
OL
Output LOW Voltage
A Port
V
CC
(V)
2.7
2.7–3.6
2.7–3.6
2.7
3.0
3.0
2.7–3.6
2.7
3.0
3.0
3.0
B Port
I
I(HOLD)
(Note 4)
I
I(OD)
(Note 4)
I
I
Bushold Input Over-Drive
Current to Change State
Input Current
Control Pins
Data Pins
I
OFF
I
PU/PD
I
OZL
I
OZL
(Note 4)
I
OZH
I
OZH
I
CCH
I
CCL
I
CCZ
I
CCZ
Power Off Leakage Current
Power Up/Down
3-STATE Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
3-STATE Output Leakage Current
Power Supply Current
Power Supply Current
Power Supply Current
Power Supply Current
Increase in Power Supply Current
(Note 7)
Note 4:
Applies to Bushold versions only (74LVTH2245).
Note 5:
An external driver must source at least the specified current to switch from LOW-to-HIGH.
Note 6:
An external driver must sink at least the specified current to switch from HIGH-to-LOW.
Note 7:
This is the increase in supply current for each input that is at the specified voltage level rather than V
CC
or GND.
T
A
40
q
C to
85
q
C
Max
Min
2.0
Units
V
V
V
V
V
V
I
I
Conditions
1.2
0.8
2.4
2.0
2.0
V
CC
0.2
0.5
0.4
0.5
0.55
0.8
0.2
75
18 mA
V
O
d
0.1V or
V
O
t
V
CC
0.1V
I
OH
I
OH
I
OH
I
OH
I
OL
I
OL
I
OL
I
OL
I
OL
I
OL
V
I
V
I
8 mA
32 mA
12 mA
100
P
A
24 mA
16 mA
32 mA
64 mA
12 mA
100
P
A
0.8V
2.0V
V
3.0
2.7
V
V
Bushold Input Minimum Drive
3.0
3.0
3.6
3.6
3.6
0
0–1.5V
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
75
500
P
A
P
A
10
(Note 5)
(Note 6)
V
I
5.5V
0V or V
CC
0V
V
CC
0.5V to 3.0V
GND or V
CC
0.5V
0.0V
3.0V
3.6V
V
I
V
I
V
I
500
r
1
5
1
P
A
r
100
r
100
5
5
5
5
10
0.19
5
0.19
0.19
0.2
P
A
P
A
P
A
P
A
P
A
P
A
P
A
mA
mA
mA
mA
mA
0V
d
V
I
or V
O
d
5.5V
V
O
V
I
V
O
V
O
V
O
V
O
I
OZH
(Note 4) 3-STATE Output Leakage Current
V
CC
V
O
d
5.5V
Outputs High
Outputs Low
Outputs Disabled
V
CC
d
V
O
d
5.5V,
Outputs Disabled
One Input at V
CC
0.6V
Other Inputs at V
CC
or GND
'
I
CC
Dynamic Switching Characteristics
Symbol
V
OLP
V
OLV
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
V
CC
(V)
3.3
3.3
(Note 8)
T
A
25
q
C
Typ
0.8
Max
Units
V
V
Conditions
C
L
50 pF, R
L
(Note 9)
(Note 9)
500
:
Min
0.8
Note 8:
Characterized in SOIC package. Guaranteed parameter, but not tested.
Note 9:
Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. Output under test held LOW.
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4
74LVT2245 • 74LVTH2245
AC Electrical Characteristics
T
A
Symbol
Parameter
V
CC
Min
t
PLH
t
PHL
t
PLH
t
PHL
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
t
OSHL
t
OSLH
t
OSHL
t
OSLH
A Port Output to Output Skew
(Note 10)
B Port Output to Output Skew
(Note 10)
Output Disable Time for A Port Output
Output Disable Time for B Port Output
Output Enable Time for A Port Output
Output Enable Time for B Port Output
Propagation Delay Data to A Port Output
Propagation Delay Data to B Port Output
1.2
1.2
1.2
1.2
1.3
1.7
1.3
1.7
2.0
2.0
2.0
2.0
C
L
40
q
C to
85
q
C
50 pF, R
L
500
:
V
CC
Min
1.2
1.2
1.2
1.2
1.3
1.7
1.3
1.7
2.0
2.0
2.0
2.0
2.7V
Max
5.1
5.1
4.0
4.0
7.3
7.3
7.1
6.7
6.5
5.7
6.5
5.1
1.0
1.0
ns
ns
ns
ns
ns
ns
ns
ns
Units
3.3V
r
0.3V
Max
4.4
4.4
3.6
3.5
6.2
6.2
5.5
5.7
5.9
5.4
5.9
5.0
1.0
1.0
Note 10:
Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t
OSHL
) or LOW-to-HIGH (t
OSLH
).
Capacitance
Symbol
C
IN
C
I/O
(Note 11)
Parameter
Conditions
V
CC
V
CC
0V, V
I
0V or V
CC
0V or V
CC
3.0V, V
O
Typical
4
8
Units
pF
pF
Input Capacitance
Input/Output Capacitance
Note 11:
Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
5
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