74VHCT573A Octal D-Type Latch with 3-STATE Outputs
January 1998
Revised April 2005
74VHCT573A
Octal D-Type Latch with 3-STATE Outputs
General Description
The VHCT573A is an advanced high speed CMOS octal
latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a Latch Enable input (LE) and an Out-
put Enable input (OE). When the OE input is HIGH, the
eight outputs are in a high impedance state.
Protection circuits ensure that 0V to 7V can be applied to
the input and output (Note 1) pins without regard to the
supply voltage. This device can be used to interface 3V to
5V systems and two supply systems such as battery back
up. This circuit prevents device destruction due to mis-
matched supply and input voltages.
Note 1:
Outputs in OFF-State.
Features
s
High speed: t
PD
7.7 ns (typ) at T
A
2.0V, V
IL
25
q
C
0.8V
s
High Noise Immunity: V
IH
s
Power Down Protection is provided on all inputs and
outputs
s
Low Noise: V
OLP
1.6V (max)
25
q
C
s
Low Power Dissipation:
I
CC
4
P
A (max) @ T
A
s
Pin and function compatible with 74HCT573
Ordering Code:
Order Number
74VHCT573AM
74VHCT573ASJ
74VHCT573AMTC
74VHCT573AN
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
IEEE/IEC
Connection Diagram
© 2005 Fairchild Semiconductor Corporation
DS500028
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74VHCT573A
Pin Descriptions
Pin Names
D
0
–D
7
LE
OE
O
0
–O
7
Description
Data Inputs
Latch Enable Input
3-STATE Output Enable Input
3-STATE Outputs
Truth Table
Inputs
OE
L
L
L
H
H HIGH Voltage Level
L LOW Voltage Level
X Immaterial
Z High Impedance
Outputs
D
H
L
X
X
O
n
H
L
O
0
Z
LE
H
H
L
X
Functional Description
The VHCT573A contains eight D-type latches with 3-
STATE output buffers. When the Latch Enable (LE) input is
HIGH, data on the D
n
inputs enters the latches. In this con-
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW the latches store the information that was present on
the D inputs, a setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers
are enabled. When OE is HIGH the buffers are in the high
impedance mode, but, this does not interfere with entering
new data into the latches.
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
74VHCT573A
Absolute Maximum Ratings
(Note 2)
Supply Voltage (V
CC
)
DC Input Voltage (V
IN
)
DC Output Voltage (V
OUT
)
(Note 3)
(Note 4)
Input Diode Current (I
IK
)
Output Diode Current (I
OK
) (Note 5)
DC Output Current (I
OUT
)
DC V
CC
/GND Current (I
CC
)
Storage Temperature (T
STG
)
Lead Temperature (T
L
)
(Soldering, 10 seconds)
260
q
C
0.5V to
7.0V
0.5V to
7.0V
0.5V to V
CC
0.5V
0.5V to
7.0V
20 mA
r
20 mA
r
25 mA
r
75 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 6)
Supply Voltage (V
CC
)
Input Voltage (V
IN
)
Output Voltage (V
OUT
)
(Note 3)
(Note 4)
Operating Temperature (T
OPR
)
Input Rise and Fall Time (t
r
, t
f
)
V
CC
5.0V
r
0.5V
0 ns/V
a
20 ns/V
Note 2:
Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
Note 3:
HIGH or LOW state. I
OUT
absolute maximum rating must be
observed.
Note 4:
When outputs are in OFF-State or when V
CC
Note 5:
V
OUT
GND, V
OUT
!
V
CC
(Outputs Active).
Note 6:
Unused inputs must be held HIGH or LOW. They may not float.
OV.
4.5V to
5.5V
0V to
5.5V
0V to V
CC
0V to 5.5V
40
q
C to
85
q
C
DC Electrical Characteristics
Symbol
V
IH
V
IL
V
OH
V
OL
I
OZ
I
IN
I
CC
I
CCT
I
OFF
Parameter
HIGH Level
Input Voltage
LOW Level
Input Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
3-STATE Output
Off-State Current
Input Leakage Current
Quiescent Supply Current
Maximum I
CC
/Input
Output Leakage Current
(Power Down State)
V
CC
(V)
4.5
5.5
4.5
5.5
4.5
4.5
4.5
4.5
5.5
0
5.5
5.5
5.5
0.0
4.40
3.94
0.0
0.1
0.36
4.50
T
A
Min
2.0
2.0
0.8
0.8
4.40
3.80
0.1
0.44
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
2.0
2.0
0.8
0.8
Min
Units
V
V
V
V
V
V
V
IN
Conditions
V
IH
I
OH
50
P
A
or V
IL
I
OH
8 mA
V
IN
V
IH
I
OL
50
P
A
or V
IL
I
OL
8 mA
V
IN
V
OUT
V
IN
V
IN
V
IN
V
OUT
V
IH
or V
IL
V
CC
or GND
5.5V or GND
V
CC
or GND
3.4V
V
CC
or GND
5.5V
r
0.25
r
0.1
4.0
1.35
0.5
r
2.5
r
1.0
40.0
1.50
5.0
P
A
P
A
P
A
mA
Other Inputs
P
A
Noise Characteristics
Symbol
V
OLP
(Note 7)
V
OLV
(Note 7)
V
IHD
(Note 7)
V
ILD
(Note 7)
Note 7:
Parameter guaranteed by design.
Parameter
Quiet Output Maximum Dynamic V
OL
Quiet Output Minimum Dynamic V
OL
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
V
CC
(V)
5.0
5.0
5.0
5.0
T
A
Typ
1.2
25
q
C
Limits
1.6
Units
V
V
V
V
C
L
C
L
C
L
C
L
Conditions
50 pF
50 pF
50 pF
50 pF
1.2
1.6
2.0
0.8
3
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74VHCT573A
AC Electrical Characteristics
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSLH
t
OSHL
C
IN
C
OUT
C
PD
Parameter
Propagation Delay Time
(LE to O
n
)
Propagation Delay Time
(D to O
n
)
3-STATE Output
Enable Time
3-STATE Output
Disable Time
Output to Output
Skew
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
Note 8:
Parameter guaranteed by design. t
OSLH
|t
PLH max
t
PLH min
|; t
OSHL
|t
PHL max
t
PHL min
|
Note 9:
C
PD
is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
operating current can be obtained by the equation: I
CC
(opr.) C
PD
* V
CC
* f
IN
I
CC
/8 (per F/F). The total C
PD
when n pcs. of the Latch operates can be cal-
culated by the equation: C
PD
(total) 14
13n.
V
CC
(V)
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
T
A
Min
25
q
C
Typ
7.7
8.5
5.1
5.9
6.3
7.1
8.8
Max
12.3
13.3
8.5
9.5
10.9
11.9
11.2
1.0
4
6
25
10
T
A
40
q
C to
85
q
C
Max
13.5
14.5
9.5
10.5
12.5
13.5
12.0
1.0
10
1.0
1.0
1.0
1.0
1.0
1.0
1.0
Min
Units
ns
ns
ns
ns
ns
pF
pF
pF
R
L
R
L
Conditions
C
L
C
L
C
L
C
L
1 k
:
C
L
C
L
1 k
:
C
L
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
(Note 8)
V
CC
V
CC
Open
5.0V
(Note 9)
AC Operating Requirements
Symbol
t
W
(H)
t
S
t
H
Parameter
Minimum Pulse Width (LE)
Minimum Setup Time
Minimum Hold Time
V
CC
(V)
5.0
r
0.5
5.0
r
0.5
5.0
r
0.5
T
A
Min
6.5
1.5
3.5
25
q
C
Typ
Max
T
A
40
q
C to
85
q
C
Max
Min
8.5
1.5
3.5
Units
ns
ns
ns
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4
74VHCT573A
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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