MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Demultiplexers
Analog Multiplexers/
MC54/74HC4051A
MC74HC4052A
MC54/74HC4053A
High–Performance Silicon–Gate CMOS
The MC54/74HC4051A, MC74HC4052A and MC54/74HC4053A utilize
silicon–gate CMOS technology to achieve fast propagation delays, low ON
resistances, and low OFF leakage currents. These analog multiplexers/
demultiplexers control analog voltages that may vary across the complete
power supply range (from VCC to VEE).
The HC4051A, HC4052A and HC4053A are identical in pinout to the
metal–gate MC14051AB, MC14052AB and MC14053AB. The Channel–Se-
lect inputs determine which one of the Analog Inputs/Outputs is to be
connected, by means of an analog switch, to the Common Output/Input.
When the Enable pin is HIGH, all analog switches are turned off.
The Channel–Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors they are compatible with LSTTL
outputs.
These devices have been designed so that the ON resistance (Ron) is
more linear over input voltage than R on of metal–gate CMOS analog
switches.
For a multiplexer/demultiplexer with channel–select latches, see
HC4351A.
•
Fast Switching and Propagation Speeds
•
Low Crosstalk Between Switches
•
Diode Protection on All Inputs/Outputs
•
Analog Power Supply Range (VCC – VEE) = 2.0 to 12.0 V
•
Digital (Control) Power Supply Range (VCC – GND) = 2.0 to 6.0 V
•
Improved Linearity and Lower ON Resistance Than Metal–Gate
Counterparts
•
Low Noise
•
In Compliance With the Requirements of JEDEC Standard No. 7A
•
Chip Complexity: HC4051A — 184 FETs or 46 Equivalent Gates
HC4052A — 168 FETs or 42 Equivalent Gates
HC4053A — 156 FETs or 39 Equivalent Gates
LOGIC DIAGRAM
MC54/74HC4051A
Single–Pole, 8–Position Plus Common Off
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
1
DEMULTIPLEXER
OUTPUTS X4
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
13
16
1
J SUFFIX
CERAMIC PACKAGE
CASE 620–10
N SUFFIX
PLASTIC PACKAGE
CASE 648–08
D SUFFIX
SOIC PACKAGE
CASE 751B–05
DW SUFFIX
SOIC WIDE PACKAGE
CASE 751G–02
DT SUFFIX
TSSOP PACKAGE
CASE 948F–01
16
1
16
1
16
1
16
1
ORDERING INFORMATION
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
MC74HCXXXXADW
MC74HCXXXXADT
Ceramic
Plastic
SOIC
SOIC Wide
TSSOP
FUNCTION TABLE – MC54/74HC4051A
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
C
L
L
L
L
H
H
H
H
X
Select
B
A
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X = Don’t Care
3
X
COMMON
OUTPUT/
INPUT
Pinout: MC54/74HC4051A
(Top View)
VCC
16
X2
15
X1
14
X0
13
X3
12
A
11
B
10
C
9
1
X4
2
X6
3
X
4
X7
5
X5
6
7
8
GND
Enable VEE
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
10/97
©
Motorola, Inc. 1997
1
REV 0
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
FUNCTION TABLE – MC74HC4052A
LOGIC DIAGRAM
MC74HC4052A
Double–Pole, 4–Position Plus Common Off
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
1
5
2
4
10
9
6
12
Control Inputs
Select
Enable
L
L
L
L
H
X = Don’t Care
B
L
L
H
H
X
A
L
H
L
H
X
ON Channels
Y0
Y1
Y2
Y3
NONE
X0
X1
X2
X3
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
ANALOG
INPUTS/OUTPUTS
Y SWITCH
3
Y
Pinout: MC74HC4052A
(Top View)
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
VCC
16
X2
15
X1
14
X
13
X0
12
X3
11
A
10
B
9
CHANNEL-SELECT
INPUTS
ENABLE
1
Y0
2
Y2
3
Y
4
Y3
5
Y1
6
7
Enable VEE
8
GND
FUNCTION TABLE – MC54/74HC4053A
LOGIC DIAGRAM
MC54/74HC4053A
Triple Single–Pole, Double–Position Plus Common Off
X0
13
X1
Y0
1
Y1
Z0
3
Z1
A
10
CHANNEL-SELECT
B
INPUTS
9
C
6
ENABLE
11
5
2
12
14
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
Select
C
B
A
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
X SWITCH
X
ANALOG
INPUTS/OUTPUTS
Y SWITCH
15
Y
COMMON
OUTPUTS/INPUTS
Z SWITCH
4
Z
X = Don’t Care
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
Pinout: MC54/74HC4053A
(Top View)
VCC
16
Y
15
X
14
X1
13
X0
12
A
11
B
10
C
9
NOTE: This device allows independent control of each switch.
Channel–Select Input A controls the X–Switch, Input B controls
the Y–Switch and Input C controls the Z–Switch
1
Y1
2
Y0
3
Z1
4
Z
5
Z0
6
7
Enable VEE
8
GND
MOTOROLA
2
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
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MAXIMUM RATINGS*
Symbol
VCC
VEE
VIS
Vin
I
Parameter
Value
Unit
V
V
V
V
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
– 0.5 to + 7.0
– 0.5 to + 14.0
– 7.0 to + 5.0
VEE – 0.5 to
VCC + 0.5
±
25
750
500
450
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
Digital Input Voltage (Referenced to GND)
DC Current, Into or Out of Any Pin
– 0.5 to VCC + 0.5
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP†
SOIC Package†
TSSOP Package†
Storage Temperature Range
mW
Tstg
TL
– 65 to + 150
260
300
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
v
v
_
C
_
C
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
Ceramic DIP
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
†Derating — Plastic DIP: – 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: – 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: – 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: – 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
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Î
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Î
Î
Symbol
VCC
VEE
VIS
Vin
Parameter
Min
2.0
2.0
Max
Unit
V
V
V
V
V
Positive DC Supply Voltage
(Referenced to GND)
(Referenced to VEE)
6.0
12.0
Negative DC Supply Voltage, Output (Referenced to
GND)
Analog Input Voltage
– 6.0
VEE
GND
VCC
VCC
1.2
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
GND
VIO*
TA
Operating Temperature Range, All Package Types
Input Rise/Fall Time
(Channel Select or Enable Inputs)
– 55
0
0
0
0
+ 125
1000
600
500
400
_
C
ns
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
* For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components. The
reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
High–Speed CMOS Logic Data
DL129 — Rev 6
3
MOTOROLA
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
DC CHARACTERISTICS — Digital Section
(Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol
S b l
VIH
Parameter
P
Minimum High–Level Input Voltage,
Channel–Select or Enable Inputs
Condition
C di i
Ron = Per Spec
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
6.0
Guaranteed Limit
–55 to 25°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
0.1
≤85°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
≤125°C
1.50
2.10
3.15
4.20
0.5
0.9
1.35
1.8
±
1.0
Unit
U i
V
VIL
Maximum Low–Level Input Voltage,
Channel–Select or Enable Inputs
Ron = Per Spec
V
Iin
ICC
Maximum Input Leakage Current,
Channel–Select or Enable Inputs
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND,
VEE = – 6.0 V
Channel Select, Enable and
VIS = VCC or GND; VEE = GND
VIO = 0 V
VEE = – 6.0
µA
µA
6.0
6.0
1
4
10
40
20
80
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
DC CHARACTERISTICS — Analog Section
Guaranteed Limit
Symbol
S b l
Ron
Parameter
P
Maximum “ON” Resistance
Condition
C di i
Vin = VIL or VIH; VIS = VCC to
VEE; IS
≤
2.0 mA
(Figures 1, 2)
Vin = VIL or VIH; VIS = VCC or
VEE (Endpoints); IS
≤
2.0 mA
(Figures 1, 2)
∆R
on
Maximum Difference in “ON”
Resistance Between Any Two
Channels in the Same Package
Maximum Off–Channel Leakage
Current, Any One Channel
Maximum Off–Channel HC4051A
Leakage Current,
HC4052A
Common Channel
HC4053A
Ion
Maximum On–Channel HC4051A
Leakage Current,
HC4052A
Channel–to–Channel HC4053A
Vin = VIL or VIH;
VIS = 1/2 (VCC – VEE);
IS
≤
2.0 mA
Vin = VIL or VIH;
VIO = VCC – VEE;
Switch Off (Figure 3)
Vin = VIL or VIH;
VIO = VCC – VEE;
Switch Off (Figure 4)
Vin = VIL or VIH;
Switch–to–Switch =
VCC – VEE; (Figure 5)
VCC
4.5
4.5
6.0
4.5
4.5
6.0
4.5
4.5
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
VEE
0.0
– 4.5
– 6.0
0.0
– 4.5
– 6.0
0.0
– 4.5
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
– 6.0
–55 to 25°C
190
120
100
150
100
80
30
12
10
0.1
0.2
0.1
0.1
0.2
0.1
0.1
≤85°C
240
150
125
190
125
100
35
15
12
0.5
2.0
1.0
1.0
2.0
1.0
1.0
≤125°C
280
170
140
230
140
115
40
18
14
1.0
4.0
2.0
2.0
4.0
2.0
2.0
µA
Ω
Unit
U i
Ω
Ioff
µA
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
MC54/74HC4051A MC74HC4052A MC54/74HC4053A
AC CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
S b l
tPLH,
tPHL
tPLH,
tPHL
tPLZ,
tPHZ
tPZL,
tPZH
Cin
CI/O
Parameter
P
Maximum Propagation Delay, Channel–Select to Analog Output
(Figure 9)
Maximum Propagation Delay, Analog Input to Analog Output
(Figure 10)
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
Maximum Propagation Delay, Enable to Analog Output
(Figure 11)
Maximum Input Capacitance, Channel–Select or Enable Inputs
Maximum Capacitance
(All Switches Off)
Analog I/O
Common O/I: HC4051A
HC4052A
HC4053A
Feedthrough
VCC
V
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Guaranteed Limit
–55 to 25°C
370
74
63
60
12
10
290
58
49
345
69
59
10
35
130
80
50
1.0
≤85°C
465
93
79
75
15
13
364
73
62
435
87
74
10
35
130
80
50
1.0
≤125°C
550
110
94
90
18
15
430
86
73
515
103
87
10
35
130
80
50
1.0
Unit
U i
ns
ns
ns
ns
pF
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High–
Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V, VEE = 0 V
CPD
Power Di i i C
P
Dissipation Capacitance (Fi
i
(Figure 13)*
HC4051A
HC4052A
HC4053A
45
80
45
pF
F
* Used to determine the no–load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
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