1. Cyclone III Device Family Overview
CIII51001-1.1
Cyclone III:
Lowest
System-Cost
FPGAs
The Cyclone
®
III FPGA family offered by Altera is a cost-optimized, memory-rich FPGA family.
Cyclone III FPGAs are built on TSMC's 65-nm low-power (LP) process technology with additional
silicon optimizations and software features to minimize power consumption. With this third
generation in the Cyclone series, Altera broadens the number of high volume, cost-sensitive
applications that can benefit from FPGAs.
This chapter contains the following sections:
■
■
■
■
“Cyclone III Device Features” on page 1–1
“Cyclone III Device Architecture” on page 1–4
“Reference and Ordering Information” on page 1–9
“Reference and Ordering Information” on page 1–9
Cyclone III
Device Features
Cyclone III devices are designed to offer low-power consumption and increased system integration
at reduced cost.
Reduced Cost
Cyclone III devices deliver the lowest device and system costs based on the following facts:
■
■
■
Staggered I/O ring to lower die area
Wide range of low cost packages
Support for low-cost serial flash and commodity parallel flash devices for configuration
Lowest-Power 65-nm FPGA
Cyclone III devices are the lowest-power 65-nm FPGAs designed via TSMC’s 65-nm low power
process and Altera’s power aware design flow. Cyclone III devices support hot-socketing operation;
therefore, unused I/O banks can be powered down when the devices to which they are connected are
turned off. Benefits of the Cyclone III device's low-power operation include:
■
■
■
Extended battery life for portable and handheld applications
Enabled operation in thermally challenged environments
Eliminated or reduced cooling system costs
Increased System Integration
Cyclone III devices provide increased system integration by offering the following features:
■
■
■
■
■
Density is up to 119,088 logic elements (LEs) and memory is up to 3.8 Mbits. Refer to
Table 1–1
on page 1–2.
High memory to logic ratio for embedded DSP applications
Highest multiplier-to-logic ratio in the industry at every density; 260 MHz multiplier
performance
High I/O count, low- and mid-range density devices for user I/O constrained applications
Up to four phase-locked loops (PLLs) provide robust clock management and synthesis for device
clocks, external system clocks, and I/O interfaces
●
Up to five outputs per PLL
●
Cascadable to save I/Os, ease PCB routing, and reduce the number of external reference
clocks needed
●
Dynamically reconfigurable to change phase shift, frequency multiplication/division, and
input frequency in-system without reconfiguring the device
Altera Corporation
July 2007
1–1
Preliminary
Cyclone III Device Family Overview
■
■
■
■
■
■
■
■
■
Support for high-speed external memory interfaces including DDR, DDR2, SDR SDRAM, and
QDRII SRAM at up to 400 Mbps
●
Auto-calibrating physical layer (PHY) feature accelerates timing closure process and
eliminates variations over process, voltage and temperature (PVT) for DDR, DDR2,
SDRAM, and QDRII SRAM interfaces
Up to 534 user I/O pins arranged in 8 I/O banks that support a wide range of industry I/O
standards
●
Up to 875 Mbps receive and 840 Mbps transmit LVDS communications
●
LVDS, RSDS
®
, mini-LVDS and PPDS
®
transmission without the use of external resistors
●
Supported I/O standards include LVTTL, LVCMOS, SSTL, HSTL, PCI, PCI-X, LVPECL,
LVDS, mini-LVDS, RSDS, and PPDS; PCI Express and Serial Rapid I/O are supported using
external PHY devices
Multi-value on-chip termination (OCT) support with calibration feature to eliminate variations
over PVT
Adjustable I/O slew rates to improve signal integrity
Support for low-cost Altera
®
serial flash and commodity parallel flash configuration devices
from Intel
Remote system upgrade feature without requiring an external controller
Dedicated Cyclic Redundancy Code (CRC) checker circuitry to detect single event upset (SEU)
conditions
Nios
®
II embedded processors for Cyclone III devices offer low cost and custom-fit embedded
processing solutions
Broad portfolio of pre-built and verified intellectual property cores from Altera and Altera
Megafunction Partners Program (AMPP
SM
) partners
RSDS and PPDS are registered trademarks of National Semiconductor.
1
Table 1–1
displays Cyclone III device family features.
Table 1–1. Cyclone III FPGA Device Family Features
Feature
Logic Elements
Memory (Kbits)
Multipliers
PLLs
Global Clock Networks
EP3C5
5,136
414
23
2
10
EP3C10 EP3C16
10,320
414
23
2
10
15,408
504
56
4
20
EP3C25 EP3C40
24,624
594
66
4
20
39,600
1,134
126
4
20
EP3C55
55,856
2,340
156
4
20
EP3C80
81,264
2,745
244
4
20
EP3C120
119,088
3,888
288
4
20
All Cyclone III devices support vertical migration within the same package. Vertical migration means
that you can migrate to devices whose dedicated pins, configuration pins, and power pins are the
same for a given package across device densities. This allows designers to optimize density and cost
as the design evolves.
1–2
Cyclone III Device Handbook, Volume 1
Altera Corporation
July 2007
Cyclone III Device Features
Table 1–2
lists the Cyclone III device package options and user I/O pin counts. The highest I/O count
in the family is delivered by the EP3C40.
Table 1–2. Cyclone III FPGA Package Options and I/O Pin Counts
Notes (1), (2), (3)
144-pin
Plastic
Enhanced
Quad Flat
Pack
(EQFP)
(5)
94
94
84
82
—
—
—
—
Device
240-pin
Plastic
Quad Flat
Pack
(PQFP)
—
—
160
148
128
—
—
—
256-pin
FineLine
Ball-Grid
Array
(FBGA)
182
182
168
156
—
—
—
—
256-pin
Ultra
FineLine
Ball-Grid
Array
(UBGA)(6)
182
182
168
156
—
—
—
—
324-pin 484-pin
FineLine FineLine
Ball-Grid Ball-Grid
Array
Array
(FBGA)
(FBGA)
—
—
—
215
195
—
—
—
—
—
346
—
331
327
295
283
484-pin
Ultra
FineLine
Ball-Grid
Array
(UBGA)(6)
—
—
346
—
331
327
295
—
780-pin
FineLine
Ball-Grid
Array
(FBGA)
—
—
—
—
535
(4)
377
429
531
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
(1)
(2)
(3)
(4)
Notes to
Table 1–2:
For more information about Device Packaging Specifications, refer to the support section of the Altera website.
(http://www.altera.com/support/devices/packaging/specifications/pkg-pin/spe-index.html).
The numbers are the maximum I/O counts (including clock input pins) supported by the device-package
combination and can be affected by the configuration scheme selected for the device.
All the packages available in lead-free and leaded options.
The EP3C40 device in the F780 package supports restricted vertical migration. Maximum user I/O is restricted to
510 I/Os if you enable migration to the EP3C120 and are using voltage referenced I/O standards. If you are not
using voltage referenced I/O standards the maximum number of I/Os can be increased.
The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must
be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity and not for
thermal purposes.
All the UBGA packages will be supported starting in Quartus II v7.1 SP1 except for the UBGA packages of EP3C16
which will be supported starting in Quartus II v7.2
(5)
(6)
Table 1–3
lists the Cyclone III FPGA package sizes.
Table 1–3. Cyclone III FPGA Package Sizes
Dimensions
Pitch (mm)
Nominal Area
(mm
2
)
Length \
Width
(mm \ mm)
Height (mm)
144-pin
EQFP
0.5
484
22 \ 22
240-pin
PQFP
0.5
1197
34.6 \
34.6
4.10
256-pin
FBGA
1.0
289
17 \ 17
256-pin
UBGA
0.8
196
14 \ 14
324-pin
FBGA
1.0
361
19 \ 19
484-pin
FBGA
1.0
529
23 \ 23
484-pin
UBGA
0.8
361
19 \ 19
780-pin
FBGA
1.0
841
29 \ 29
1.60
1.55
2.20
2.20
2.60
2.20
2.60
Altera Corporation
July 2007
1–3
Cyclone III Device Handbook, Volume 1
Cyclone III Device Family Overview
Cyclone III devices are available in up to three speed grades: –6, –7, and –8 (–6 is the fastest).
Table 1–4
shows Cyclone III device speed grade offerings.
Table 1–4. Cyclone III Devices Speed Grades
Device
EP3C5
EP3C10
EP3C16
EP3C25
EP3C40
EP3C55
EP3C80
EP3C120
144-pin
EQFP
–
7,
–
8
–
7,
–
8
–
7,
–
8
–
7,
–
8
—
—
—
—
240-pin
PQFP
—
—
256-pin
FBGA
256-pin
UBGA
324-pin
FBGA
—
—
—
484-pin
FBGA
—
—
484-pin
UBGA
—
—
780-pin
FBGA
—
—
—
—
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
—
—
—
—
—
—
—
—
–
8
–
8
–
8
—
—
—
–
6,
–
7,
–
8
–
6,
–
7,
–
8
—
—
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
—
—
—
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
6,
–
7,
–
8
–
7,
–
8
—
–
7,
–
8
Cyclone III
Device
Architecture
Cyclone III FPGAs include a customer-defined feature set optimized for cost-sensitive applications
and offer a wide range of density, memory, embedded multiplier, I/O, and packaging options.
Cyclone III FPGAs support numerous external memory interfaces and I/O protocols common in
high-volume applications.
Figure 1–1
shows a floor plan view of the Cyclone III device architecture.
Figure 1–1. Cyclone III Device Architecture Overview
Note (1)
Staggered I/O Ring
Up to 3.8 M-bit of
M9K Embedded
Memory Blocks
Up to 288 Embedded
Multipliers for
High-Throughput
DSP
Up to 119,088 LEs
Up to 535
User I/O With
Integrated OCT
200-MHz
Memory
Interfaces
Dynamically
Configurable PLLs
Note to
Figure 1–1:
(1)
EP3C5 and EP3C10 have only 2 PLLs
1–4
Cyclone III Device Handbook, Volume 1
Altera Corporation
July 2007
Cyclone III Device Architecture
LEs and LABs
The logic array block (LAB) consists of 16 logic elements (LEs) and a LAB-wide control block. An LE
is the smallest unit of logic in the Cyclone III device architecture. Each LE has four inputs, a 4-input
look-up-table (LUT), a register, and output logic. The 4-input LUT is a function generator that can
implement any function of four variables.
f
For more information, refer to the
Logic Elements and Logic Array Blocks
chapter in volume 1 of the
Cyclone III Device Handbook.
MultiTrack Interconnect
In the Cyclone III device architecture, interconnections between LEs, LABs, M9K memory blocks,
embedded multipliers, and device I/O pins are provided by the MultiTrack interconnect structure
which is a fabric of routing wires. The MultiTrack interconnect structure consists of
performance-optimized routing lines of different speeds used for inter- and intra-design block
connectivity. The Quartus
®
II software automatically optimizes designs by placing the critical path
on the fastest interconnects.
f
For more information, refer to the
MultiTrack Interconnect
chapter in volume 1 of the
Cyclone III
Device Handbook.
Memory Blocks
Each Cyclone III FPGA M9K memory block provides up to 9 kbits of on-chip memory capable of
operation at up to 260 MHz. The embedded memory structure consists of columns of M9K memory
blocks that can be configured as RAM, first-in first-out (FIFO) buffers, or ROM. Cyclone III memory
blocks are optimized for applications such as high throughput packet processing, high definition
(HD) line buffers for video processing functions, and embedded processor program and data storage.
The Quartus II software allows you to take advantage of M9K memory blocks by instantiating
memory using a dedicated megafunction wizard, or by inferring memory directly from VHDL or
Verilog source code.
Table 1–5. Cyclone III Memory Modes
Port Mode
Single Port
Simple Dual Port
True Dual Port
Port Width Configuration
x1, x2, x4, x8, x9, x16, x18, x32 and x36
x1, x2, x4, x8, x9, x16, x18, x32 and x36
x1, x2, x4, x8, x9, x16 and x18
f
For more information, refer to the
Memory Blocks
chapter in volume 1 of the
Cyclone III Device
Handbook.
Embedded Multipliers and Digital Signal Processing Support
Cyclone III devices offer up to 288 embedded multiplier blocks and support the following modes: one
individual 18 × 18-bit multiplier per block, or two individual 9 × 9-bit multipliers per block. The
Quartus II software includes megafunctions that are used to control the mode of operation of the
embedded multiplier blocks based on user parameter settings. Multipliers can also be inferred
directly from VHDL or Verilog source code.
In addition to embedded multipliers, Cyclone III FPGAs include a combination of on-chip resources
and external interfaces that make them ideal to increase performance, reduce system cost, and lower
the power consumption of digital signal processing (DSP) systems. Cyclone III FPGAs can be used
alone or as DSP device co-processors to improve price-to-performance ratios of DSP systems.
Altera Corporation
July 2007
1–5
Cyclone III Device Handbook, Volume 1
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