ICS9148F-12LF-T datasheet, PDF

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ICS9148F-12LF-T: DescriptionClock Generator, PDSO48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size384KB，18 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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ICS9148F-12LF-T Overview

Clock Generator, PDSO48

ICS9148F-12LF-T Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Reach Compliance Code	unknown
JESD-30 code	R-PDSO-G48
JESD-609 code	e3
Humidity sensitivity level	1
Number of terminals	48
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	SSOP
Encapsulate equivalent code	SSOP48,.4
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, SHRINK PITCH
power supply	3.3 V
Certification status	Not Qualified
Maximum slew rate	100 mA
Nominal supply voltage	3.3 V
surface mount	YES
Temperature level	COMMERCIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	GULL WING
Terminal pitch	0.635 mm
Terminal location	DUAL
Base Number Matches	1

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Integrated

Circuit

Systems, Inc.

ICS9148-12

Frequency Timing Generator for Pentium/Pro

or Transmeta

Efficeon

General Description

ICS9148-12

is a Clock Synthesizer chip for Pentium/Pro-

based Desktop/Notebook systems or Transmeta Efficeon

Mobile systems.

Features include four strong CPU, seven PCI and eight

SDRAM clocks. Two reference outputs are available

equal to the crystal frequency. Stronger drive CPUCLK

outputs typically provide greater than 1 V/ns slew rate into

20pF loads. This device meets rise and fall requirements

with 2 loads per CPU output (ie, one clock to CPU and NB

chipset, one clock to two L2 cache inputs).

PWR_DWN# pin allows low power mode by stopping

crystal OSC and PLL stages. For optional power

management, CPU_STOP# can stop CPU (0:3) clocks

and PCI_STOP# will stop PCICLK (0:5) clocks. CPU and

IOAPIC output buffer strength controlled by CPU 3.3_2.5#

pin to match VDDL voltage.

PCICLK outputs typically provide better than 1V/ns slew

rate into 30pF loads while maintaining 50±5% duty cycle.

The REF clock outputs typically provide better than 0.5V/

ns slew rates.

The

ICS9148-12

accepts a 14.318MHz reference crystal

or clock as its input and runs on a 3.3V core supply.

Features

•

CPU outputs are stronger drive for multiple loads

per pin (ie CPU and NB on one pin)

Generates system clocks for CPU, IOAPIC,

SDRAM, PCI, plus 14.314 MHz REF(0:1), USB,

Plus Super I/O

Supports single or dual processor systems

C serial configuration interface provides output

clock disabling and other functions

MODE input pin selects optional power

management input control pins

Two fixed outputs separately selectable as 24 or

48MHz

Separate 2.5V and 3.3V supply pins

2.5V or 3.3V outputs: CPU, IOAPIC

3.3V outputs: SDRAM, PCI, REF, 48/24 MHz

CPU 3.3_2.5# logic pin to adjust output strength

No power supply sequence requirements

Uses external 14.318MHz crystal

48 pin 300 mil SSOP and 240 mil TSSOP

Output enable register

for serial port control:

1 = enable

0 = disable

Pin Configuration

Block Diagram

48-Pin SSOP & TSSOP

Functionality

VDD (1:4) 3.3V±10%, VDDL1, 2 2.5±5% or 3.3±10% 0-70

Crystal (X1, X2) = 14.31818 MHz

SEL

0123I—07/18/05

CPUCLK, SDRAM

(MHz)

66.6

PCICLK

(MHz)

33.3

Transmeta and Efficeon are trademarks of Transmeta Corporation.

Pentium/Pro is a trademark of Intel Corporation.

ICS9148F-12LF-T Related Products

	ICS9148F-12LF-T	ICS9148G-12LF-T	ICS9148G-12-T	ICS9148F-12-T	ICS9148F-12T	9148AG-12LFT
Description	Clock Generator, PDSO48	Clock Generator, PDSO48	Clock Generator, PDSO48	Clock Generator, PDSO48	Clock Generator, PDSO48	Clock Generator
Is it Rohs certified?	conform to	conform to	incompatible	incompatible	incompatible	conform to
Reach Compliance Code	unknown	unknown	not_compliant	unknown	not_compliant	compliant
JESD-609 code	e3	e3	e0	e0	e0	e3
Terminal surface	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Tin/Lead (Sn85Pb15)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn85Pb15)	Matte Tin (Sn) - annealed
JESD-30 code	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	R-PDSO-G48	-
Humidity sensitivity level	1	1	1	-	1	1
Number of terminals	48	48	48	48	48	-
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	SSOP	TSSOP	TSSOP	SSOP	SSOP	-
Encapsulate equivalent code	SSOP48,.4	TSSOP48,.3,20	TSSOP48,.3,20	SSOP48,.4	SSOP48,.4	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	-
power supply	3.3 V	3.3 V	2.5/3.3,3.3 V	3.3 V	3.3 V	-
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-
Maximum slew rate	100 mA	100 mA	-	100 mA	100 mA	-
Nominal supply voltage	3.3 V	3.3 V	-	3.3 V	3.3 V	-
surface mount	YES	YES	YES	YES	YES	-
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	-
Terminal form	GULL WING	GULL WING	GULL WING	GULL WING	GULL WING	-
Terminal pitch	0.635 mm	0.5 mm	0.5 mm	0.635 mm	0.635 mm	-
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	-
Base Number Matches	1	1	1	1	1	-

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