VT-701
Temperature Compensated Crystal Oscillator
Previous Vectron Model VTC2
VT-701
Description
Vectron’s VT-701 Temperature Compensated Crystal Oscillator (TCXO) is a quartz stabilized, clipped sine wave output, analog
temperature compensated oscillator, operating off either a 3.3 or 5.0 volt supply in a hermetically sealed 5x7 ceramic package.
Features
•
•
•
•
•
•
CMOS Output
Output Frequencies to 27 MHz
Fundamental Crystal Design
Optional VCXO Function available
Gold over nickel contact pads
Hermetically Sealed Ceramic SMD package
•
•
•
•
•
•
•
•
Applications
FPGA’s
A/D’s, D/A’s
Broadband Access Head End
Wireless Communications
Base Stations
Point to point radios
Broadband Access
Test Equipment
• Product is compliant to RoHS directive
and fully compatible with lead free assembly
Block Diagram
V
DD
Crystal
Output
Analog
Temperature
Comp.
Vcontrol or NC
Gnd
Page1
Table 1. Electrical Performance
Parameter
Output Frequency
Supply Voltage
1
, Ordering
Option
Supply Current
Operating Temperature, Ordering
Option
Stability Over T
OP
,
Ordering Option
Initial Accuracy, “No Adjust” Option
Power Supply Stability
Load Stability
Aging
Pull Range,
ordering option
Control Voltage to reach Pull Range
Control Voltage Impedance
Output Level
2
Output Logic High
Output Logic Low
Output Logic High Drive
Output Logic Low Drive
Output Load
Phase Noise, 10.000MHz
10Hz
100Hz
1kHz
10kHz
100kHz
Enable Disable
3
, Output Enbaled
Output Disabled
Start Up Time
1. The V-701 power supply pin should be filtered, eg, a 0.1 and 0.01uf capacitor
2. The Output is DC coupled
3. Output is Enabled if E/D is left open
V
IH
V
IL
0.3*
VDD
2
ms
-92
-116
-137
-149
-154
0.7*V
DD
V
OH
V
OL
I
OH
I
OL
TPR
0.5
1
0.8*V
DD
0.1*V
DD
-4
4
15
±5, ±8, ±10, ±12
2.5
Symbol
f
O
V
DD
I
DD
T
OP
Min.
5
Typ
+3.3 or +5.0
Max
27
10
Units
MHz
Vdc
mA
°C
ppm
ppm
ppm
ppm
ppm/yr
ppm
V
Mohm
V
V
mA
mA
pF
dBc/Hz
0/55, -10/60, -20/70, -30/80, -40/85
±0.5, ±1.0, ±.5, ±2.0, ±2.5, ±3.0, ±4.0, ±5.0
±1.0
±0.3
±0.2
±1.0
Outline Drawing
7.0±01
2.0 max
0.4±0.1
Recommended Pad Layout
6.0
1.8
1.4 1.0
5.0±0.1
FREQUENCY
Date Code
1.4
1.3
2.54
1.2
1.4
0.8 typ
Pad Layout mm
Table 2. Pinout
1.27±0.1
1.0±0.1
Pin #
1
2,3,4
Symbol
V
C
NC
GND
f
O
NC
E/D
V
DD
Function
TCXO Control Voltage or Ground
Make No Connection
Electrical and Lid Ground
Output Frequency
Make No Connection
Enable Disable
Supply Voltage
2.54±0.1
0.8±0.1
5
6
7,8
Dimensions in mm
9
10
Page2
1.0±0.1
0.6±0.1
Test Circuit
t
R
V
OH
50%
I
C
V
C
1
+
-
Period
2
15pF
V
OL
On Time
t
F
I
DD
4
+
V
DD
-
.1µF
.01µF
3
VCXO Function
S
VCXO Feature:
The VT-701 can be ordered with a VCXO function for applications were it will be used in a PLL, or the output frequency
needs fine tune or calibration adjustments. This is a high impedance input , 1Mohm, and can be driven with an op-amp or terminated with
adjustable resistors etc.
Pin 1 should not be left floating on the VCXO optional device.
“No Adjust” Option:
In applications were the VT-701 will not be used in a PLL , or the output frequency does not need fine tune
adjustments, the best device to use would be a VT-701-xxx-xxx0. By using the “no adjust” option, the circuit is simplified as Vc does not
need to be adjusted or set to a predetermined voltage and pin 1 should be grounded (pin 1 can be left open but should not be set to a
voltage such as an RF signal or power supply voltage.
Maximum Ratings
S
Absolute Maximum Ratings and Handling Precautions
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied or any other
excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended
periods may adversely affect device reliability.
Although ESD protection circuitry has been designed into the VT-701, proper precautions should be taken when handling and mounting,
VI employs a Human Body Model and Charged Device Model for ESD susceptibility testing and design evaluation.
ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry standard has been adopted for
Phase Noise Graph
the CDM a standard resistance of 1.5kOhms and capacitance of 100pF is widely used and therefor can be used for comparison purposes.
Table 3. Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Control Voltage
ESD, Human Body Model
ESD, Charged Device Model
Symbol
T
STORE
V
DD
V
C
Rating
-55/125
6
0/V
DD
1500
1000
Unit
ºC
V
V
V
V
Table 4. Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Fine and Gross Leak
Resistance to Solvents
Moisture Sensitivity Level
Contact Pads
Condition
MIL-STD-883 Method 2002
MIL-STD-883 Method 2007
MIL-STD-883 Method 1010
MIL-STD-883 Method 2003
MIL-STD-883 Method 1014
MIL-STD-883 Method 2015
MSL1
Gold over Nickel
Page3
IR Compliance
S
Suggested IR Profile
Devices are built using lead free epoxy and can be subjected to
standard lead free IR reflow conditions shown in Table 5. Contact
pads are gold over nickel and lower maximum temperatures can also
be used, such as 220C.
Table 5. Reflow Profile
Parameter
PreHeat Time
Ramp Up
Time above 217°C
Time to Peak Temperature
Time at 260°C
Time at 240°C
Ramp down
Symbol
ts
R
UP
tL
tAMB-P
tP
tP2
R
DN
Value
200 sec Max
3°C/sec Max
150 sec Max
480 sec Max
30 sec Max
60 sec Max
6°C/sec Max
Tape & Reel
Table 6. Tape and Reel Information
Tape Dimensions (mm)
W
16
F
7.5
Do
1.5
Po
4
P1
8
A
180
B
1.5
Reel Dimensions (mm)
C
13
D
20.2
N
60
W1
16.4
W2
20.4
#/Reel
1000
Page4
Table 7. Standard Frequencies (MHz)
5.000*
19.440
6.400*
19.800
8.192
20.000
10.000
24.000
Standard Frequencies
12.500*
25.000
12.800
26.000
13.000*
27.000
16.384
19.200
20.000
Ordering Information
VT-701- E A G - X X X A- xxMxxxxxxx
Frequency in MHz
Product
TCXO
Package
5x7
Voltage Options
D: +5.0 Vdc ±5%,
E: +3.3 Vdc ±5%,
Output
A: CMOS
Temp Range
R: 0 /55°C
K: -10/60°C
J: -20/70°C
G: -30/80°C
E: -40/85°C
Tuning
0: Fixed, No tuning
A: ±5ppm
B: ±8ppm
C: ±10ppm
D: ±12ppm
Stability
507: ±0.5ppm
106: ±1ppm
156: ±1.5ppm
206: ±2.0ppm
256: ±2.5ppm
306: ±3.0ppm
356: ±3.5ppm
406: ±4.0ppm
506: ±5.0ppm
Note: Not all combination of options are available
and * notes limited temperature stability.
Example: VT-701-EAG-206A-19M2000000
*
Add
_SNPBDIP
for tin lead solder dip
Example: VT-701-EAG-206A-19M2000000_SNPBDIP
Revision History
Revision Date
August 10, 2018
Approved
FB
Description
Rev 0.4: Updated logo and contact information, added “SNPBDIP” ordering option
Page5
Embedded System
京公网安备 11010802033920号
EEWORLD
