0
R
XA2C256 CoolRunner-II
Automotive CPLD
0
0
DS555 (v1.2) June 22, 2009
Product Specification
-
Hot pluggable
Features
•
AEC-Q100 device qualification and full PPAP support
available in both I-grade and extended temperature
Q-grade
Guaranteed to meet full electrical specifications over
T
A
= –40°C to +105°C with T
J
Maximum = +125°C
(Q-grade)
Optimized for 1.8V systems
Industry’s best 0.18 micron CMOS CPLD
- Optimized architecture for effective logic synthesis.
Refer to the CoolRunner™-II family data sheet for
architecture description.
- Multi-voltage I/O operation — 1.5V to 3.3V
Available in multiple package options
- 100-pin VQFP with 80 user I/O
- 144-pin TQFP with 118 user I/O
- Pb-free only for all packages
Advanced system features
- Fastest in system programming
·
1.8V ISP using IEEE 1532 (JTAG) interface
- IEEE1149.1 JTAG Boundary Scan Test
- Optional Schmitt-trigger input (per pin)
- Unsurpassed low power management
·
DataGATE enable (DGE) signal control
- Two separate I/O banks
- RealDigital 100% CMOS product term generation
- Flexible clocking modes
·
Optional DualEDGE triggered registers
·
Clock divider (divide by 2, 4, 6, 8, 10, 12, 14, 16)
·
CoolCLOCK
- Global signal options with macrocell control
·
Multiple global clocks with phase selection per
macrocell
·
Multiple global output enables
·
Global set/reset
- Advanced design security
- PLA architecture
·
Superior pinout retention
·
100% product term routability across function
block
- Open-drain output option for Wired-OR and LED
drive
- Optional bus-hold, 3-state or weak pull-up on
selected I/O pins
- Optional configurable grounds on unused I/Os
- Mixed I/O voltages compatible with 1.5V, 1.8V,
2.5V, and 3.3V logic levels
WARNING: Programming temperature range of
T
A
= 0°C to +70°C.
•
Description
The CoolRunner-II Automotive 256-macrocell device is
designed for both high performance and low power applica-
tions. This lends power savings to high-end communication
equipment and high speed to battery operated devices. Due
to the low power stand-by and dynamic operation, overall
system reliability is improved.
This device consists of sixteen Function Blocks inter-con-
nected by a low power Advanced Interconnect Matrix (AIM).
The AIM feeds 40 true and complement inputs to each
Function Block. The Function Blocks consist of a 40 by 56
P-term PLA and 16 macrocells which contain numerous
configuration bits that allow for combinational or registered
modes of operation.
Additionally, these registers can be globally reset or preset
and configured as a D or T flip-flop or as a D latch. There
are also multiple clock signals, both global and local product
term types, configured on a per macrocell basis. Output pin
configurations include slew rate limit, bus hold, pull-up,
open drain and programmable grounds. A Schmitt-trigger
input is available on a per input pin basis. In addition to stor-
ing macrocell output states, the macrocell registers may be
configured as “direct input” registers to store signals directly
from input pins.
Clocking is available on a global or Function Block basis.
Three global clocks are available for all Function Blocks as a
synchronous clock source. Macrocell registers can be indi-
vidually configured to power up to the zero or one state. A
global set/reset control line is also available to asynchro-
nously set or reset selected registers during operation.
Additional local clock, synchronous clock-enable, asynchro-
nous set/reset and output enable signals can be formed
using product terms on a per-macrocell or per-Function
Block basis.
A DualEDGE flip-flop feature is also available on a per mac-
rocell basis. This feature allows high performance synchro-
nous operation based on lower frequency clocking to help
reduce the total power consumption of the device.
Circuitry has also been included to divide one externally
supplied global clock (GCK2) by eight different selections.
This yields divide by even and odd clock frequencies.
•
•
•
•
© 2006–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS555 (v1.2) June 22, 2009
Product Specification
www.xilinx.com
1
R
XA2C256 CoolRunner-II Automotive CPLD
Due to this technology, Xilinx CoolRunner-II Automotive
CPLDs achieve both high-performance and low power oper-
ation.
The use of the clock divide (division by 2) and DualEDGE
flip-flop gives the resultant CoolCLOCK feature.
DataGATE is a method to selectively disable inputs of the
CPLD that are not of interest during certain points in time.
By mapping a signal to the DataGATE function, lower power
can be achieved due to reduction in signal switching.
Another feature that eases voltage translation is I/O bank-
ing. Two I/O banks are available on the CoolRunner-II Auto-
motive 256-macrocell device that permit easy interfacing to
3.3V, 2.5V, 1.8V, and 1.5V devices.
The CoolRunner-II Automotive 256-macrocell CPLD is I/O
compatible with various I/O standards (see
Table 1).
This
device is also 1.5V I/O compatible with the use of Schmitt-
trigger inputs.
Supported I/O Standards
The CoolRunner-II Automotive 256-macrocell device fea-
tures LVCMOS and LVTTL I/O implementations. See
Table 1
for I/O standard voltages. The LVTTL I/O standard is
a general-purpose EIA/JEDEC standard for 3.3V applica-
tions that use an LVTTL input buffer and Push-Pull output
buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V
applications. CoolRunner-II Automotive CPLDs are also
1.5V I/O compatible with the use of Schmitt-trigger inputs.
Table 1:
I/O Standards for XA2C256
IOSTANDARD Attribute
LVTTL
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
(1)
Output V
CCIO
3.3
3.3
2.5
1.8
1.5
Input V
CCIO
3.3
3.3
2.5
1.8
1.5
RealDigital Design Technology
Xilinx® CoolRunner-II Automotive CPLDs are fabricated on
a 0.18 micron process technology which is derived from
leading edge FPGA product development. CoolRunner-II
Automotive CPLDs employ RealDigital, a design technique
that makes use of CMOS technology in both the fabrication
and design methodology. RealDigital design technology
employs a cascade of CMOS gates to implement sum of
products instead of traditional sense amplifier methodology.
75
(1) LVCMOS15 requires Schmitt-trigger inputs.
ICC (mA)
50
25
0
0
50
100
150
Frequency (MHz)
DS555_01_092106
Figure 1:
I
CC
vs Frequency
Table 2:
I
CC
vs Frequency (LVCMOS 1.8V T
A
= 25°C)
(1)
Frequency (MHz)
0
Typical I
CC
(mA)
0.021
30
11.68
50
19.40
70
27.01
100
38.18
120
45.54
150
56.32
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block).
DS555 (v1.2) June 22, 2009
Product Specification
www.xilinx.com
2
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XA2C256 CoolRunner-II Automotive CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
CCIO
V
JTAG(2)
V
CCAUX
V
IN(1)
V
TS(1)
T
STG(3)
T
J
Description
Supply voltage relative to ground
Supply voltage for output drivers
JTAG input voltage limits
JTAG input supply voltage
Input voltage relative to ground
Voltage applied to 3-state output
Storage Temperature (ambient)
Junction Temperature
Value
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to 4.0
–65 to +150
+125
Units
V
V
V
V
V
V
°C
°C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easiest to achieve. During transitions,
the device pins may undershoot to –2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
2. Valid over commercial temperature range.
3. For soldering guidelines and thermal considerations, see the
Device Package User Guide.
For Pb-free packages, see
XAPP427.
Recommended Operating Conditions
Symbol
V
CC
Parameter
Supply voltage for internal logic and
input buffers
Industrial T
A
= –40°C to +85°C
Q-Grade T
A
= –40°C to +105°C
T
J
Maximum = +125°C
Min
1.7
1.7
3.0
2.3
1.7
1.4
1.7
Max
1.9
1.9
3.6
2.7
1.9
1.6
3.6
Units
V
V
V
V
V
V
V
V
CCIO
Supply voltage for output drivers @ 3.3V operation
Supply voltage for output drivers @ 2.5V operation
Supply voltage for output drivers @ 1.8V operation
Supply voltage for output drivers @ 1.5V operation
V
CCAUX
JTAG programming
DC Electrical Characteristics
(Over Recommended Operating Conditions)
Symbol
I
CCSB
I
CCSB
I
CC
C
JTAG
C
CLK
C
IO
I
IL(2)
I
IH(2)
Parameter
Standby current Industrial
Standby current Q-grade
Dynamic current
JTAG input capacitance
Global clock input capacitance
I/O capacitance
Input leakage current
I/O High-Z leakage
Test Conditions
V
CC
= 1.9V, V
CCIO
= 3.6V
V
CC
= 1.9V, V
CCIO
= 3.6V
f = 1 MHz
f = 50 MHz
f = 1 MHz
f = 1 MHz
f = 1 MHz
V
IN
= 0V or V
CCIO
to 3.9V
V
IN
= 0V or V
CCIO
to 3.9V
Typical
54
54
-
-
-
-
-
-
-
Max.
300
2.5
3.0
30
10
12
10
±10
±10
Units
μA
mA
mA
mA
pF
pF
pF
μA
μA
Notes:
1. 16-bit up/down, resettable binary counter (one counter per function block) tested at V
CC
= V
CCIO
= 1.9V
DS555 (v1.2) June 22, 2009
Product Specification
www.xilinx.com
3
R
XA2C256 CoolRunner-II Automotive CPLD
LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications
Symbol
V
CCIO
V
IH
V
IL
V
OH
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage,
Industrial grade
High level output voltage,
Q-grade
V
OL
High level output voltage,
Industrial grade
High level output voltage,
Q-grade
Test Conditions
-
-
-
I
OH
= –8 mA, V
CCIO
= 3V
I
OH
= –0.1 mA, V
CCIO
= 3V
I
OH
= –4 mA, V
CCIO
= 3V
I
OH
= –0.1 mA, V
CCIO
= 3V
I
OL
= 8 mA, V
CCIO
= 3V
I
OL
= 0.1 mA, V
CCIO
= 3V
I
OL
= 4 mA, V
CCIO
= 3V
I
OL
= 0.1 mA, V
CCIO
= 3V
Min.
3.0
2
–0.3
V
CCIO
– 0.4V
V
CCIO
– 0.2V
V
CCIO
– 0.4V
V
CCIO
– 0.2V
-
-
-
-
Max.
3.6
3.9
0.8
-
-
-
-
0.4
0.2
0.4
0.2
Units
V
V
V
V
V
V
V
V
V
V
V
LVCMOS 2.5V DC Voltage Specifications
Symbol
V
CCIO
V
IH
V
IL
V
OH
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage,
Industrial grade
High level output voltage, Q-grade
V
OL
High level output voltage,
Industrial grade
High level output voltage, Q-grade
Test Conditions
-
-
-
I
OH
= –8 mA, V
CCIO
= 2.3V
I
OH
= –0.1 mA, V
CCIO
= 2.3V
I
OH
= –4 mA, V
CCIO
= 2.3V
I
OH
= –0.1 mA, V
CCIO
= 2.3V
I
OL
= 8 mA, V
CCIO
= 2.3V
I
OL
= 0.1 mA, V
CCIO
= 2.3V
I
OL
= 4 mA, V
CCIO
= 2.3V
I
OL
= 0.1 mA, V
CCIO
= 2.3V
Min.
2.3
1.7
–0.3
V
CCIO
– 0.4V
V
CCIO
– 0.2V
V
CCIO
– 0.4V
V
CCIO
– 0.2V
-
-
-
-
Max.
2.7
V
CCIO
+ 0.3
(1)
Units
V
V
V
V
V
V
V
V
V
V
V
0.7
-
-
-
-
0.4
0.2
0.4
0.2
1. The V
IH
Max value represents the JEDEC specification for LVCMOS25. The CoolRunner-II input buffer can tolerate up
to 3.9V without physical damage.
LVCMOS 1.8V DC Voltage Specifications
Symbol
V
CCIO
V
IH
V
IL
V
OH
Parameter
Input source voltage
High level input voltage
Low level input voltage
High level output voltage,
Industrial grade
High level output voltage, Q-grade
Test Conditions
-
-
-
I
OH
= –8 mA, V
CCIO
= 1.7V
I
OH
= –0.1 mA, V
CCIO
= 1.7V
I
OH
= –4 mA, V
CCIO
= 1.7V
I
OH
= –0.1 mA, V
CCIO
= 1.7V
Min.
1.7
0.65 x V
CCIO
–0.3
V
CCIO
– 0.45
V
CCIO
– 0.2
V
CCIO
– 0.45
V
CCIO
– 0.2
Max.
1.9
V
CCIO
+ 0.3
(1)
Units
V
V
V
V
V
V
V
0.35 x V
CCIO
-
-
-
-
DS555 (v1.2) June 22, 2009
Product Specification
www.xilinx.com
4
R
XA2C256 CoolRunner-II Automotive CPLD
Symbol
V
OL
Parameter
High level output voltage, Industrial
grade
High level output voltage, Q-grade
Test Conditions
I
OL
= 8 mA, V
CCIO
= 1.7V
I
OL
= 0.1 mA, V
CCIO
= 1.7V
I
OL
= 4 mA, V
CCIO
= 1.7V
I
OL
= 0.1 mA, V
CCIO
= 1.7V
Min.
-
-
-
-
Max.
0.45
0.2
0.45
0.2
Units
V
V
V
V
1. The V
IH
Max value represents the JEDEC specification for LVCMOS18. The CoolRunner-II input buffer can tolerate up
to 3.9V without physical damage.
LVCMOS 1.5V DC Voltage Specifications
(1)
Symbol
V
CCIO
V
T+
V
T-
V
OH
High level output voltage,
Industrial grade
High level output voltage, Q-grade
V
OL
High level output voltage,
Industrial grade
High level output voltage, Q-grade
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
-
-
-
I
OH
= –8 mA, V
CCIO
= 1.4V
I
OH
= –0.1 mA, V
CCIO
= 1.4V
I
OH
= –4 mA, V
CCIO
= 1.4V
I
OH
= –0.1 mA, V
CCIO
= 1.4V
I
OL
= 8 mA, V
CCIO
= 1.4V
I
OL
= 0.1 mA, V
CCIO
= 1.4V
I
OL
= 4 mA, V
CCIO
= 1.4V
I
OL
= 0.1 mA, V
CCIO
= 1.4V
Notes:
1.
Hysteresis used on 1.5V inputs.
Min.
1.4
0.5 x V
CCIO
0.2 x V
CCIO
V
CCIO
– 0.45
V
CCIO
– 0.2
V
CCIO
– 0.45
V
CCIO
– 0.2
-
-
-
-
Max.
1.6
0.8 x V
CCIO
0.5 x V
CCIO
-
-
-
-
0.4
0.2
0.4
0.2
Units
V
V
V
V
V
V
V
V
V
V
V
Schmitt Trigger Input DC Voltage Specifications
Symbol
V
CCIO
V
T+
V
T-
Parameter
Input source voltage
Input hysteresis threshold voltage
Test Conditions
-
-
-
Min.
1.4
0.5 x V
CCIO
0.2 x V
CCIO
Max.
3.9
0.8 x V
CCIO
0.5 x V
CCIO
Units
V
V
V
AC Electrical Characteristics Over Recommended Operating Conditions
-7
Symbol
T
PD1
T
PD2
T
SUD
T
SU1
T
SU2
T
HD
T
H
T
CO
Parameter
Propagation delay single p-term
Propagation delay OR array
Direct input register clock setup time
Setup time (single p-term)
Setup time (OR array)
Direct input register hold time
P-term hold time
Clock to output
Min.
-
-
3.0
2.8
3.3
0
0
-
Max.
7.0
7.5
-
-
-
-
-
6.0
Min.
-
-
3.0
3.4
3.9
0.4
0.4
-
-8
Max.
7.0
7.5
-
-
-
-
-
6.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
DS555 (v1.2) June 22, 2009
Product Specification
www.xilinx.com
5
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