IC41C4100
IC41LV4100
1M x 4 (4-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
FEATURES
Extended Data-Out (EDO) Page Mode access cycle
TTL compatible inputs and outputs; tristate I/O
Refresh Interval: 1024 cycles /16 ms
Refresh Mode:
RAS-Only, CAS-before-RAS
(CBR),
Hidden
• Single power supply:
5V ± 10% (IC41C4100)
3.3V ± 10% (IC41LV4100)
• Industrail Temperature Range -40
o
C to 85
o
C
•
•
•
•
DESCRIPTION
The
ICSI
IC41C4100 and IC41LV4100 is a 1,048,576 x 4-bit
high-performance CMOS Dynamic Random Access Memories.
The IC41C4100 offer an accelerated cycle access called EDO
Page Mode. EDO Page Mode allows 1024 random accesses
within a single row with access cycle time as short as 12 ns per
4-bit word.
These features make the IC41C4100and IC41LV4100 ideally
suited for, digital signal processing, high-performance audio
systems, and peripheral applications.
The IC41C4100 is packaged in a 20-pin 300mil SOJ and 300mil
TSOP-2.
KEY TIMING PARAMETERS
Parameter
Max.
RAS
Access Time (t
RAC
)
Max.
CAS
Access Time (t
CAC
)
Max. Column Address Access Time (t
AA
)
Min. EDO Page Mode Cycle Time (t
PC
)
Min. Read/Write Cycle Time (t
RC
)
-35
35
10
18
12
60
-50
50
14
25
20
90
-60
60
15
30
25
110
Unit
ns
ns
ns
ns
ns
PIN CONFIGURATION
20 (26) Pin SOJ, TSOP-2
I/O0
I/O1
WE
RAS
A9
1
2
3
4
5
26
25
24
23
22
GND
I/O3
I/O2
CAS
OE
PIN DESCRIPTIONS
A0-A9
I/O0-3
WE
OE
RAS
CAS
Vcc
Address Inputs
Data Inputs/Outputs
Write Enable
Output Enable
Row Address Strobe
Column Address Strobe
Power
Ground
No Connection
A0
A1
A2
A3
VCC
9
10
11
12
13
18
17
16
15
14
A8
A7
A6
A5
A4
GND
NC
2
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
IC41C4100
IC41LV4100
Functional Description
The IC41C4100 and IC41LV4100 is a CMOS DRAM
optimized for high-speed bandwidth, low power applica-
tions. During READ or WRITE cycles, each bit is uniquely
addressed through the 20 address bits. These are entered
10 bits (A0-A9) at a time. The row address is latched by the
Row Address Strobe (RAS). The column address is latched
by the Column Address Strobe (CAS)
.
Refresh Cycle
To retain data, 1024 refresh cycles are required in each
16 ms period. There are two ways to refresh the memory.
1. By clocking each of the 1024 row addresses (A0 through
A9) with
RAS
at least once every 16 ms. Any read, write,
read-modify-write or
RAS-only
cycle refreshes the ad-
dressed row.
2. Using a
CAS-before-RAS
refresh cycle.
CAS-before-
RAS
refresh is activated by the falling edge of
RAS,
while holding
CAS
LOW. In
CAS-before-RAS
refresh
cycle, an internal 10-bit counter provides the row ad-
dresses and the external address inputs are ignored.
CAS-before-RAS
is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Memory Cycle
A memory cycle is initiated by bring
RAS
LOW and it is
terminated by returning both
RAS
and
CAS
HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum t
RAS
time has expired. A new
cycle must not be initiated until the minimum precharge
time t
RP
, t
CP
has elapsed.
Extended Data Out Page Mode
EDO page mode operation permits all 1024 columns within
a selected row to be randomly accessed at a high data rate.
In EDO page mode read cycle, the data-out is held to the
next
CAS
cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the
CAS
cycle time becomes shorter. Therefore,
in EDO page mode, the timing margin in read cycle is
larger than that of the fast page mode even if the
CAS
cycle
time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS
cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write opera-
tions during one
RAS
cycle, but the performance is
equivalent to that of the fast page mode in that case.
Read Cycle
A read cycle is initiated by the falling edge of
CAS
or
OE,
whichever occurs last, while holding
WE
HIGH. The
column address must be held for a minimum time specified
by t
AR
. Data Out becomes valid only when t
RAC
, t
AA
, t
CAC
and t
OE
are all satisfied. As a result, the access time is
dependent on the timing relationships between these
parameters.
Write Cycle
A write cycle is initiated by the falling edge of
CAS
and
WE,
whichever occurs last. The input data must be valid
at or before the falling edge of
CAS
or
WE,
whichever
occurs first.
Power-On
After application of the V
CC
supply, an initial pause of
200 µs is required followed by a minimum of eight initial-
ization cycles (any combination of cycles containing a
RAS
signal).
During power-on, it is recommended that
RAS
track with
V
CC
or be held at a valid V
IH
to avoid current surges.
Integrated Circuit Solution Inc.
DR027-0A 09/05/2001
5
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