V827565N24SBTGD3 datasheet, PDF

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V827565N24SBTGD3: DescriptionDDR DRAM Module, 128MX72, 0.65ns, CMOS, DIMM-184; Categorystorage storage; File Size253KB，16 Pages; ManufacturerProMOS Technologies Inc

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V827565N24SBTGD3 Overview

DDR DRAM Module, 128MX72, 0.65ns, CMOS, DIMM-184

V827565N24SBTGD3 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.65 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
memory density	9663676416 bit
Memory IC Type	DDR DRAM MODULE
memory width	72
Number of functions	1
Number of ports	1
Number of terminals	184
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX72
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
self refresh	YES
Maximum standby current	0.18 A
Maximum slew rate	6.48 mA
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
Base Number Matches	1

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V827565N24SA

1GB 184-PIN DDR REGISTERED ECC DIMM

128M x 72

Features

■

184 Pin Registered 134,217,728 x 72 bit

Organization DDR SDRAM Modules

■

Utilizes High Performance 128M x 4 DDR

SDRAM in TSOPII and FBGA Package

■

Single +2.5V (± 0.2V) Power Supply

Single +2.6V (± 0.1V) Power Supply for DDR400

■

Programmable CAS Latency, Burst Length, and

Wrap Sequence (Sequential & Interleave)

■

Auto Refresh (CBR) and Self Refresh

■

All Inputs, Outputs are SSTL-2 Compatible

■

8192 Refresh Cycles every 64 ms

■

Serial Presence Detect (SPD)

■

DDR SDRAM Performance

Component Used

-6

-7

Module Speed

Description

The V827565N24SA memory module is

organized 134,217,728 x 72 bits in a 184 pin

memory module. The 128M x 72 memory module

uses 18 ProMOS 128M x 4 DDR SDRAM. The x72

modules are ideal for use in high performance

computer systems where increased memory

density and fast access times are required.

-75

-8

(PC400B)

166

(PC333)

Units

MHz

CLK

Clock Frequency

166

143

133

125

Clock Frequency (max.)

(PC266A) (PC266B)

200

(PC333)

(max.)

(PC200)

Clock Access Time

7.5

Clock Cycle Time CAS Latency = 2

CAS Latency = 2.5

Clock Cycle Time CAS Latency = 2.5

Clock Cycle Time CAS Latency = 3

7.5

Module Speed

tRCD parameter

A1t

RCD

PC1600 (100MHz @ CL2)

B0 t

PC2100Bparameter @ CL2.5)

tRP (133MHz

PC2100A (133MHz @ CL2)

PC2700 (166MHz @ CL2.5)

V827565N24SA Rev. 1.0 March 2005

V827565N24SBTGD3 Related Products

	V827565N24SBTGD3	V827565N24SBEWC0	V827565N24SBEWD3	V827565N24SBTGC0
Description	DDR DRAM Module, 128MX72, 0.65ns, CMOS, DIMM-184	DDR DRAM Module, 128MX72, 0.7ns, CMOS, GREEN, DIMM-184	DDR DRAM Module, 128MX72, 0.65ns, CMOS, GREEN, DIMM-184	DDR DRAM Module, 128MX72, 0.7ns, CMOS, DIMM-184
Is it Rohs certified?	incompatible	conform to	conform to	incompatible
Parts packaging code	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM-184
Contacts	184	184	184	184
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
Maximum access time	0.65 ns	0.7 ns	0.65 ns	0.7 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz	166 MHz	200 MHz	166 MHz
I/O type	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184
memory density	9663676416 bit	9663676416 bit	9663676416 bit	9663676416 bit
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	72	72	72	72
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	184	184	184	184
word count	134217728 words	134217728 words	134217728 words	134217728 words
character code	128000000	128000000	128000000	128000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	128MX72	128MX72	128MX72	128MX72
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM184	DIMM184	DIMM184	DIMM184
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192
self refresh	YES	YES	YES	YES
Maximum standby current	0.18 A	0.18 A	0.18 A	0.18 A
Maximum slew rate	6.48 mA	6.3 mA	6.48 mA	6.3 mA
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.3 V	2.3 V	2.3 V	2.3 V
Nominal supply voltage (Vsup)	2.5 V	2.5 V	2.5 V	2.5 V
surface mount	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
Base Number Matches	1	1	1	-

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