72P51539L5BB8 datasheet, PDF - EEWORLD Datasheet

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72P51539L5BB8: DescriptionPBGA-256, Reel; Categorystorage storage; File Size830KB，87 Pages; ManufacturerIDT (Integrated Device Technology)

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72P51539L5BB8 Overview

PBGA-256, Reel

72P51539L5BB8 Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	PBGA
package instruction	BGA, BGA256,16X16,40
Contacts	256
Manufacturer packaging code	BB256
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	3.6 ns
Maximum clock frequency (fCLK)	200 MHz
period time	5 ns
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
memory density	589824 bit
Memory IC Type	OTHER FIFO
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	256
word count	16384 words
character code	16000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	16KX36
Exportable	YES
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	1.8 V
Certification status	Not Qualified
Maximum seat height	3.5 mm
Maximum standby current	0.1 A
Maximum slew rate	0.15 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	17 mm
Base Number Matches	1

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1.8V MULTI-QUEUE FLOW-CONTROL DEVICES

(32 QUEUES) 36 BIT WIDE CONFIGURATION

589,824 bits

1,179,648 bits

2,359,296 bits

4,718,592 bits

IDT72P51539

IDT72P51549

IDT72P51559

IDT72P51569

FEATURES

•

Choose from among the following memory density options:

IDT72P51539



Total Available Memory = 589,824 bits

IDT72P51549



Total Available Memory = 1,179,648 bits

IDT72P51559



Total Available Memory = 2,359,296 bits

IDT72P51569



Total Available Memory = 4,718,592 bits

Configurable from 1 to 32 Queues

Default configuration of 32 or 16 symmetrical queues

Default multi-queue device configurations

– IDT72P51539: 512 x 36 x 32Q

– IDT72P51549: 1,024 x 36 x 32Q

– IDT72P51559: 2,048 x 36 x 32Q

– IDT72P51569: 4,096 x 36 x 32Q

Default configuration can be augmented via the queue address

bus

Number of queues and individual queue sizes may be

configured at master reset though serial programming

200 MHz High speed operation (5ns cycle time)

3.6ns access time

Independent Read and Write access per queue

•

User Selectable Bus Matching Options:

– x36 in to x36 out

– x18 in to x36 out

– x9 in to x36 out

– x36in to x18out

– x18 in to x18 out

– x9 in to x18 out

– x36in to x9out

– x18 in to x9 out

– x9 in to x9 out

User selectable I/O: 1.5V HSTL, 1.8V eHSTL, or 2.5V LVTTL

100% Bus Utilization, Read and Write on every clock cycle

Selectable First Word Fall Through (FWFT) or IDT standard

mode of operation

Ability to operate on packet or word boundaries

Mark and Re-Write operation

Mark and Re-Read operation

Individual, Active queue flags (OR /

EF, IR

FF, PAE, PAF, PR)

8 bit parallel flag status on both read and write ports

Direct or polled operation of flag status bus

Expansion of up to 256 queues and/or 32Mb logical configura-

tion using up to 8 multi-queue devices in parallel

JTAG Functionality (Boundary Scan)

Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

HIGH Performance submicron CMOS technology

Industrial temperature range (-40°C to +85°C) is available

Green parts available, see Ordering Information

FUNCTIONAL BLOCK DIAGRAM

MULTI-QUEUE FLOW-CONTROL DEVICE

WADEN

FSTR

WRADD

WEN

WCLK

WCS

READ CONTROL

Q31

RADEN

ESTR

RDADD

WRITE CONTROL

Q30

REN

RCLK

RCS

Q29

Din

Qout

x36, 18 or x9

DATA IN

x36, x18 or x9

DATA OUT

READ FLAGS

EF/OR

PAE

PAEn

WRITE FLAGS

FF/IR

PAF

PAFn

PRn

6715 drw01

IDT and the IDT logo are trademarks of Integrated Device Technology, Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

2005

AUGUST 2005

DSC-6715/3

IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES

(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Table of Contents

Features ........................................................................................................................................................................................................................ 1

Description ................................................................................................................................................................................................................... 5

Pin configuration ......................................................................................................................................................................................................... 7

Detailed Description .................................................................................................................................................................................................... 8

Pin Descriptions ......................................................................................................................................................................................................... 10

Pin number table ........................................................................................................................................................................................................ 16

Recommended DC operating conditions ................................................................................................................................................................ 17

Absolute maximum ratings ........................................................................................................................................................................................ 17

DC electrical characteristics ..................................................................................................................................................................................... 18

AC electrical characteristics ...................................................................................................................................................................................... 20

Functional description .............................................................................................................................................................................................. 22

Serial Programming .............................................................................................................................................................................................. 23

Default Programming ............................................................................................................................................................................................ 23

Parallel Programming ........................................................................................................................................................................................... 23

Queue Description ..................................................................................................................................................................................................... 25

Configuration of the IDT Multi-queue flow-control device ....................................................................................................................................... 25

Standard mode operation ..................................................................................................................................................................................... 26

Read Queue Selection and Read Operation ......................................................................................................................................................... 27

Switching Queues on the Write Port ...................................................................................................................................................................... 29

Switching Queues on the Read Port ..................................................................................................................................................................... 31

Flag Description ......................................................................................................................................................................................................... 42

PAFn Flag Bus Operation ..................................................................................................................................................................................... 42

Full Flag Operation ............................................................................................................................................................................................... 42

Empty or Output Ready Flag Operation (EF/OR) .................................................................................................................................................. 42

Almost Full Flag .................................................................................................................................................................................................... 43

Almost Empty Flag ................................................................................................................................................................................................ 43

Packet Ready Flag ............................................................................................................................................................................................... 47

Packet Mode Demarcation bits .............................................................................................................................................................................. 49

JTAG Interface ............................................................................................................................................................................................................ 82

JTAG AC electrical characteristics ............................................................................................................................................................................ 86

Ordering Information ................................................................................................................................................................................................. 87

List of Tables

Table 1 — Device programming mode comparison ........................................................................................................................................................ 22

Table 2 — Setting the queue programming mode during master reset ............................................................................................................................. 22

Table 3 — Mode Configuration ...................................................................................................................................................................................... 25

Table 4 — Write Address Bus, WRADD[7:0] ................................................................................................................................................................... 26

Table 5 — Read Address Bus, RDADD[7:0] .................................................................................................................................................................. 27

Table 6 — Write Queue Switch Operation ...................................................................................................................................................................... 30

Table 7 — Read Queue Switch Operation ..................................................................................................................................................................... 32

Table 8 — Same Queue Switch ..................................................................................................................................................................................... 32

Table 9 — Flag operation boundaries and Timing .......................................................................................................................................................... 45

Table 10 — Packet Mode Valid Byte for x36 bit word configuration ................................................................................................................................. 48

Table 11 — Bus-Matching Set-Up .................................................................................................................................................................................. 52

AUGUST 4, 2005

IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES

(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures

Figure 1. Multi-Queue Flow-Control Device Block Diagram .............................................................................................................................................. 6

Figure 2a. AC Test Load ................................................................................................................................................................................................ 19

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 19

Figure 3. Reference Signals .......................................................................................................................................................................................... 22

Figure 4. Device Programming Hierarchy ..................................................................................................................................................................... 24

Figure 5. IDT Standard mode illustrated (Read Port) ..................................................................................................................................................... 25

Figure 6. First Word Fall Through (FWFT) mode illustrated (Read Port) ........................................................................................................................ 25

Figure 7. Write Port Switching Queues Signal Sequence ................................................................................................................................................ 29

Figure 8. Switching Queues Bus Efficiency ..................................................................................................................................................................... 29

Figure 9. Simultaneous Queue Switching ....................................................................................................................................................................... 30

Figure 10. Read Port Switching Queues Signal Sequence ............................................................................................................................................. 31

Figure 11. Switching Queues Bus Efficiency ................................................................................................................................................................... 31

Figure 12. Simultaneous Queue Switching ..................................................................................................................................................................... 32

Figure 13. MARK and Re-Write Sequence .................................................................................................................................................................... 33

Figure 14. MARK and Re-Read Sequence ................................................................................................................................................................... 33

Figure 15. MARKing a Queue in Packet Mode - Write Queue MARK ............................................................................................................................. 34

Figure 16. MARKing a Queue in Packet Mode - Read Queue MARK ............................................................................................................................ 34

Figure 17. UN-MARKing a Queue in Packet Mode - Write Queue UN-MARK ................................................................................................................ 35

Figure 18. UN-MARKing a Queue in Packet Mode - Read Queue UN-MARK ............................................................................................................... 35

Figure 19. MARKing a Queue in FIFO Mode - Write Queue MARK ............................................................................................................................... 37

Figure 20. MARKing a Queue in FIFO Mode - Read Queue MARK .............................................................................................................................. 37

Figure 21. UN-MARKing a Queue in FIFO Mode - Write Queue UN-MARK .................................................................................................................. 38

Figure 22. UN-MARKing a Queue in FIFO Mode - Read Queue UN-MARK ................................................................................................................. 38

Figure 23. Leaving a MARK active on the Write Port ...................................................................................................................................................... 39

Figure 24. Leaving a MARK active on the Read Port ..................................................................................................................................................... 39

Figure 25. Inactivating a MARK on the Write Port Active ................................................................................................................................................. 40

Figure 26. Inactivating a MARK on the Read Port Active ................................................................................................................................................ 40

Figure 27. 36bit to 36bit word configuration .................................................................................................................................................................... 49

Figure 28. 36bit to 18bit word configuration .................................................................................................................................................................... 49

Figure 29. 36bit to 9bit word configuration ...................................................................................................................................................................... 49

Figure 30. 18bit to 36bit word configuration .................................................................................................................................................................... 50

Figure 31. 18bit to 18bit word configuration .................................................................................................................................................................... 50

Figure 32. 18bit to 9bit word configuration ...................................................................................................................................................................... 50

Figure 33. 9bit to 36bit word configuration ...................................................................................................................................................................... 51

Figure 34. 9bit to 18bit word configuration ...................................................................................................................................................................... 51

Figure 35. 9bit to 9bit word configuration ........................................................................................................................................................................ 51

Figure 36. Bus-Matching Byte Arrangement ................................................................................................................................................................... 53

Figure 37. Master Reset ................................................................................................................................................................................................ 54

Figure 38. Default Programming .................................................................................................................................................................................... 55

Figure 39. Parallel Programming ................................................................................................................................................................................... 56

Figure 40. Queue Programming via Write Address Bus .................................................................................................................................................. 57

Figure 41. Queue Programming via Read Address Bus ................................................................................................................................................. 57

Figure 42. Serial Port Connection for Serial Programming .............................................................................................................................................. 57

Figure 43. Serial Programming ...................................................................................................................................................................................... 58

Figure 44. Write Queue Select, Write Operation and Full Flag Operation ........................................................................................................................ 59

Figure 45. Write Queue Select and Mark ....................................................................................................................................................................... 60

Figure 46. Write Operations in First Word Fall Through mode ....................................................................................................................................... 61

Figure 47. Full Flag Timing in Expansion Configuration .................................................................................................................................................. 62

Figure 48. Read Queue Select, Read Operation (IDT mode) ......................................................................................................................................... 63

Figure 49. Read Queue Select, Read Operation (FWFT mode) ..................................................................................................................................... 64

Figure 50. Read Queue Select and Mark (IDT mode) .................................................................................................................................................... 65

Figure 51. Output Ready Flag Timing (In FWFT Mode) ................................................................................................................................................. 66

Figure 52. Read Queue Selection with Read Operations (IDT mode) ............................................................................................................................. 67

Figure 53. Read Queue Select, Read Operation and OE Timing .................................................................................................................................... 68

Figure 54. Writing in Packet Mode during a Queue change ............................................................................................................................................ 69

AUGUST 4, 2005

IDT72P51539/72P51549/72P51559/72P51569 1.8V, MQ FLOW-CONTROL DEVICES

(32 QUEUES) 36 BIT WIDE CONFIGURATION 589, 824, 1,179,648, 2,359,296, and 4,718,592

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

List of Figures (Continued)

Figure 55. Reading in Packet Mode during a Queue change ......................................................................................................................................... 70

Figure 56. Writing Demarcation Bits (Packet Mode) ........................................................................................................................................................ 71

Figure 57. Data Output (Receive) Packet Mode of Operation ......................................................................................................................................... 72

Figure 58. Almost Full Flag Timing and Queue Switch .................................................................................................................................................... 73

Figure 59. Almost Full Flag Timing ................................................................................................................................................................................. 73

Figure 60. Almost Empty Flag Timing and Queue Switch (FWFT mode) ......................................................................................................................... 74

Figure 61. Almost Empty Flag Timing ............................................................................................................................................................................. 74

Figure 62.

PAEn/PRn

- Direct Mode - Status Word Selection ......................................................................................................................................... 75

Figure 63.

PAFn

- Direct Mode - Status Word Selection ................................................................................................................................................. 75

Figure 64.

PAEn

- Direct Mode, Flag Operation ............................................................................................................................................................. 76

Figure 65.

PAFn

- Direct Mode, Flag Operation ............................................................................................................................................................. 77

Figure 66.

PAFn

Bus - Polled Mode .............................................................................................................................................................................. 78

Figure 67. Expansion using ID codes ............................................................................................................................................................................ 79

Figure 68. Expansion using

WCS/RCS

......................................................................................................................................................................... 80

Figure 69. Expansion Connection Read Chip Select (RCS) ........................................................................................................................................... 81

Figure 70. Expansion Connection Write Chip Select (WCS) ........................................................................................................................................... 81

Figure 71. Boundary Scan Architecture ......................................................................................................................................................................... 82

Figure 72. TAP Controller State Diagram ....................................................................................................................................................................... 83

Figure 73. Standard JTAG Timing .................................................................................................................................................................................. 86

AUGUST 4, 2005

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