AS7C251MPFS36A-133BCN datasheet, PDF

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AS7C251MPFS36A-133BCN: DescriptionStandard SRAM, 1MX36, 10ns, CMOS, PBGA165, LEAD FREE, BGA-165; Categorystorage storage; File Size579KB，23 Pages; ManufacturerALSC [Alliance Semiconductor Corporation]; Environmental Compliance

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AS7C251MPFS36A-133BCN Overview

Standard SRAM, 1MX36, 10ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C251MPFS36A-133BCN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Parts packaging code	BGA
package instruction	LBGA, BGA165,11X15,40
Contacts	165
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Maximum access time	10 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	R-PBGA-B165
JESD-609 code	e3/e6
length	17 mm
memory density	37748736 bit
Memory IC Type	STANDARD SRAM
memory width	36
Number of functions	1
Number of terminals	165
word count	1048576 words
character code	1000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	1MX36
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5 V
Certification status	Not Qualified
Maximum seat height	1.46 mm
Maximum standby current	0.06 A
Minimum standby current	2.38 V
Maximum slew rate	0.325 mA
Maximum supply voltage (Vsup)	2.625 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	PURE MATTE TIN/TIN BISMUTH
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	15 mm
Base Number Matches	1

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April 2004

AS7C251MPFS32A

AS7C251MPFS36A

2.5V 1M

32/36 pipelined burst synchronous SRAM

Features

•

Organization: 1,048,576 words × 32 or 36 bits

Fast clock speeds to 200 MHz in LVTTL/LVCMOS

Fast clock to data access: 3.1/3.4/3.8 ns

Fast OE access time: 3.1/3.4/3.8 ns

Fully synchronous register-to-register operation

Single register flow-through mode

Single-cycle deselect

- Dual-cycle deselect also available (AS7C252MPFD18A,

AS7C251MPFD32A/ AS7C251MPFD36A)

Asynchronous output enable control

Available in 100-pin TQFP and 165-ball BGA packages

Individual byte write and global write

Multiple chip enables for easy expansion

•

2.5V core power supply

Linear or interleaved burst control

Snooze mode for reduced power-standby

Common data inputs and data outputs

Boundary scan using IEEE 1149.1 JTAG function

NTD™

pipelined architecture available

(AS7C252MNTD18A, AS7C251MNTD32A/

AS7C251MNTD36A)

•

1 NTD™ is a trademark of Alliance Semiconductor Corporation. All

trademarks mentioned in this document are the property of their

respective owners.

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

A[19:0]

CLK

CLR

Burst logic

Address

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Byte write

registers

CLK

Enable

CLK

1M × 32/36

Memory

array

32/36

GWE

BWE

CE0

CE1

CE2

Output

registers

CLK

Input

registers

CLK

Power

down

Enable

delay

CLK

32/36

DQ[a:d]

Selection guide

Minimum cycle time

Maximum clock frequency

Maximum pipelined clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

-200

200

3.1

400

120

-167

167

3.4

350

110

-133

7.5

133

3.8

325

100

Units

MHz

4/26/04, v.1.0

Alliance Semiconductor

1 of 23

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