DPS2MK32MKV3-25B datasheet, PDF

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DPS2MK32MKV3-25B: DescriptionSRAM Module, 2MX32, 25ns, CMOS, CPGA66, 1.190 X 1.190 INCH, 0.660 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66; Categorystorage storage; File Size610KB，6 Pages; ManufacturerB&B Electronics Manufacturing Company

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DPS2MK32MKV3-25B Overview

SRAM Module, 2MX32, 25ns, CMOS, CPGA66, 1.190 X 1.190 INCH, 0.660 INCH HEIGHT, VERSA STACK, CERAMIC, PGA-66

DPS2MK32MKV3-25B Parametric

Parameter Name	Attribute value
Parts packaging code	PGA
package instruction	PGA,
Contacts	66
Reach Compliance Code	unknown
ECCN code	3A001.A.2.C
Maximum access time	25 ns
Other features	USER CONFIGURABLE AS 8M X 8
Spare memory width	16
JESD-30 code	S-CPGA-P66
memory density	67108864 bit
Memory IC Type	SRAM MODULE
memory width	32
Number of functions	1
Number of ports	1
Number of terminals	66
word count	2097152 words
character code	2000000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	2MX32
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Package shape	SQUARE
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Certification status	Not Qualified
Maximum seat height	16.764 mm
Minimum standby current	2 V
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
Base Number Matches	1

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8Mx8/4Mx16/2Mx32, 20 - 45ns, PGA

30A128-18

64 Megabit High Speed CMOS SRAM

DPS2MK32MKV3

PRELIMINARY

DESCRIPTION:

The DPS2MK32MKV3 ‘’VERSA-STACK’’ module is a

revolutionary new high speed memory subsystem using

Dense-Pac Microsystems’ ceramic Stackable Leadless Chip

Carriers (SLCC) mounted on a co-fired ceramic substrate. It

offers 64 Megabits of SRAM in a package envelope of 1.190 x

1.190 x 0.660 inches.

The DPS2MK32MKV3 contains sixteen individual 512K x 8

SRAMs, packaged in their own hermetically sealed SLCCs

making the module suitable for commercial, industrial and

military applications.

By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a

higher board density of memory than available with

conventional through-hole, surface mount, module, or hybrid

techniques.

FEATURES:

•

Organizations Available:

READ:

WRITE:

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 32

2 Meg x 32, 4 Meg x 16

or 8 Meg x 8

•

Access Times:

20*, 25, 35, 45ns

•

Fully Static Operation

- No clock or refresh required

•

Low Power Dissipation

•

Single +5V Power Supply,

•

±10%

Tolerance

TTL Compatible

Common Data Inputs and Outputs

Low Data Retention Current

66-Pin PGA Special ‘’VERSA-STACK’’

Package with Compatable Footprint

Commercial and Industrial only.

PIN-OUT DIAGRAM

PIN NAMES

A0 - A18

I/O0 - I/O31

CE0 - CE3

WE0 - WE3

N.C.

Address Inputs

Data Input/Output

Low Chip Enables

Write Enables

Output Enable

Power (+5V)

Ground

No Connect

30A128-18

REV. A

This document contains information on a product that is currently released

to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the

right to change products or specifications herein without prior notice.

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