PRELIMINARY
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
36-Mbit (1M x 36/2M x 18/512K x 72) Pipelined SRAM
with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 200 and 167MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 2.5V power supply
• 2.5V/1.8V I/O operation
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• CY7C1460AV25 and CY7C1462AV25 available in 100
TQFP and 165 fBGA packages CY7C1464AV25 available
in 209-Ball fBGA package
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 are
2.5V, 1M x 36 / 2M x 18 /Synchronous pipelined burst SRAMs
with No Bus Latency™ (NoBL™) logic, respectively. They are
designed to support unlimited true back-to-back Read/Write
operations with no wait states. The CY7C1460AV25/
CY7C1462AV25/CY7C1464AV25 are equipped with the
advanced (NoBL) logic required to enable consecutive
Read/Write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput
of data in systems that require frequent Write/Read transitions.
The CY7C1460AV25/ CY7C1462AV25/ CY7C1464AV25 are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Write operations are controlled by the
Byte Write Selects (BW
a
–BW
h
for CY7C1464AV25,
BW
a
–BW
d
for CY7C1460AV25 and BW
a
–BW
b
for
CY7C1462AV25) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1460AV25 (1M x 36)
A0, A1, A
MODE
CLK
CEN
ADDRESS
REGISTER 0
A1
A1'
D1
Q1
A0
A0'
BURST
D0
Q0
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 1
WRITE ADDRESS
REGISTER 2
C
ADV/LD
BW
a
BW
b
BW
c
BW
d
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
a
DQP
b
DQP
c
DQP
d
E
INPUT
REGISTER 1
E
INPUT
REGISTER 0
E
OE
CE1
CE2
CE3
ZZ
READ LOGIC
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document #: 38-05354 Rev. **
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 12, 2004
PRELIMINARY
209-Ball PBGA
CY7C1464AV25 (512K x 72)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
DQg
DQg
DQg
DQg
DQPg
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPd
DQd
DQd
DQd
DQd
CY7C1460AV25
CY7C1462AV25
CY7C1464AV25
2
DQg
DQg
DQg
DQg
DQPc
DQc
DQc
DQc
DQc
NC
DQh
DQh
DQh
DQh
DQPh
DQd
DQd
DQd
DQd
3
A
BWS
c
BWS
h
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
CLK
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TMS
4
CE
2
BWS
g
BWS
d
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDI
5
A
NC
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
NC/72M
A
A
6
ADV/LD
WE
CE
1
OE
V
DD
NC
NC
NC
NC
CEN
NC
NC
NC
ZZ
V
DD
MODE
A
A1
A0
7
A
A
NC
NC
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
V
SS
V
DD
NC
A
A
A
8
CE
3
BWS
b
BWS
e
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
NC
A
A
TDO
9
A
BWS
f
BWS
a
V
SS
V
DDQ
V
SS
V
DDQ
V
SSQ
V
DDQ
NC
V
DDQ
V
SS
V
DDQ
V
SS
V
DDQ
V
SS
NC
A
TCK
10
DQb
DQb
DQb
DQb
DQPf
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPa
DQe
DQe
DQe
DQe
11
DQb
DQb
DQb
DQb
DQPb
DQf
DQf
DQf
DQf
NC
DQa
DQa
DQa
DQa
DQPe
DQe
DQe
DQe
DQe
Pin Definitions
Pin Name
A0
A1
A
BW
a
BW
b
BW
c
BW
d
BW
e
BW
f
BW
g
BW
h
WE
ADV/LD
I/O Type
Input-
Synchronous
Input-
Synchronous
Pin Description
Address Inputs used to select one of the address locations.
Sampled at the rising edge of
the CLK.
Byte Write Select Inputs, active LOW.
Qualified with WE to conduct writes to the SRAM.
Sampled on the rising edge of CLK. BW
a
controls DQ
a
and DQP
a
, BW
b
controls DQ
b
and DQP
b
,
BW
c
controls DQ
c
and DQP
c
, BW
d
controls DQ
d
and DQP
d
, BW
e
controls DQ
e
and DQP
e,
BW
f
controls DQ
f
and DQP
f,
BW
g
controls DQ
g
and DQP
g,
BW
h
controls DQ
h
and DQP
h
.
Input-
Synchronous
Input-
Synchronous
Write Enable Input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This
signal must be asserted LOW to initiate a write sequence.
Advance/Load Input used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a
new address can be loaded into the device for an access. After being deselected, ADV/LD should
be driven LOW in order to load a new address.
Document #: 38-05354 Rev. **
Page 5 of 27
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