NB7L1008M
2.5V / 3.3V 1:8 CML Fanout
Multi−Level Inputs w/ Internal
Termination
Description
The NB7L1008M is a high performance differential 1:8 Clock/Data
fanout buffer. The NB7L1008M produces eight identical output copies
of Clock or Data operating up to 6 GHz or 10.7 Gb/s, respectively. As
such, the NB7L1008M is ideal for SONET, GigE, Fiber Channel,
Backplane and other Clock/Data distribution applications. The
differential inputs incorporate internal 50
W
termination resistors that
are accessed through the VT pin. This feature allows the NB7L1008M
to accept various logic standards, such as LVPECL, CML, LVDS,
LVCMOS or LVTTL logic levels. The V
REFAC
reference output can
be used to rebias capacitor−coupled differential or single−ended input
signals. The 1:8 fanout design was optimized for low output skew
applications. The NB7L1008M is a member of the GigaComm™
family of high performance clock products.
Features
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MARKING
32
DIAGRAM
1
1
32
QFN32
MN SUFFIX
CASE 488AM
A
WL
YY
WW
G
NB7L
1008M
AWLYYWWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Input Data Rate > 12 Gb/s Typical
Data Dependent Jitter < 20 ps
Maximum Input Clock Frequency > 8 GHz Typical
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:8 CML Outputs, < 25 ps max
Multi−Level Inputs, accepts LVPECL, CML, LVDS
160 ps Typical Propagation Delay
45 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV Peak−to−Peak, Typical
Operating Range: V
CC
= 2.375 V to 3.6 V, GND = 0 V
Internal Input Termination Resistors, 50
W
V
REFAC
Reference Output
QFN−32 Package, 5 mm x 5 mm
−40°C
to +85°C Ambient Operating Temperature
These are Pb−Free Devices
SIMPLIFIED LOGIC DIAGRAM
Q0
Q0
Q1
Q1
Q2
Q2
IN
VT
50W
50W
IN
V
REFAC
Q3
Q3
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
ORDERING INFORMATION
See detailed ordering and shipping information on page 9 of
this data sheet.
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 1
1
Publication Order Number:
NB7L1008M/D
NB7L1008M
Exposed Pad
(EP)
VCC
32
VCC
GND
IN
VT
VREFAC
IN
GND
VCC
1
2
3
4
5
6
7
8
9
VCC
31
30
29
28
27
26
25
24
23
22
21
GND
VCC
Q3
Q3
Q4
Q4
VCC
NB7L1008M
VCC
Q0
Q0
Q1
Q1
Q2
Q2
20
19
18
17
GND
10
Q7
11
Q7
12
Q6
13
Q6
14
Q5
15
Q5
16
VCC
Figure 1. 32−Lead QFN Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
3, 6
4
2, 7 17,24
1, 8, 9, 16, 18,
23, 25, 32
31, 30, 29, 28,
27, 26, 22, 21,
20, 19, 15, 14,
13, 12, 11, 10
5
−
Name
IN, IN
VT
GND
V
CC
Q0, Q0, Q1,
Q1, Q2, Q2,
Q3, Q3, Q4,
Q4, Q5, Q5,
Q6, Q6, Q7, Q7
VREFAC
EP
−
CML
I/O
LVPECL, CML,
LVDS Input
Description
Non−inverted / Inverted Differential Clock/Data Input. Note 1
Internal 50
W
Termination Pin for IN and IN
Negative Supply Voltage, Note 2
Positive Supply Voltage, Note 2
Non−inverted / Inverted Differential Output. Note 1
Output Voltage Reference for Capacitor−Coupled Inputs, only
The Exposed Pad (EP) on the QFN−24 package bottom is thermally connected to
the die for improved heat transfer out of package. The exposed pad must be at-
tached to a heat−sinking conduit. The pad is electrically connected to GND and is
recommended to be electrically connected to GND on the PC board.
1. In the differential configuration when the input termination pin (V
T
) is connected to a common termination voltage or left open, and if no signal
is applied on IN/IN, then the device will be susceptible to self−oscillation. Qn/Qn outputs have internal 50
W
source termination resistors.
2. All V
CC
and GND pins must be externally connected to the same power supply voltage to guarantee proper device operation.
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2
NB7L1008M
Table 2. ATTRIBUTES
Characteristics
ESD Protection
Human Body Model
Machine Model
Value
> 2 kV
> 200 V
Level 1
UL 94 V−0 @ 0.125 in
263
Moisture Sensitivity (Note 3) Indefinite Time of the Drypack
QFN−32
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
3. For additional information, refer to Application Note AND8003/D.
Oxygen Index: 28 to 34
Table 3. MAXIMUM RATINGS
Symbol
V
CC
V
IN
V
INPP
I
IN
I
out
I
VFREFAC
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
Input Voltage
Differential Input Voltage |IN
−
IN|
Input Current Through R
T
(50
W
Resistor)
Output Current
V
REFAC
Sink/Source Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 4)
TGSD 51−6 (2S2P Multilayer Test Board) with Filled Thermal Vias
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
Standard
Board
QFN−32
QFN−32
QFN−32
Continuous
Surge
Parameter
Condition 1
GND = 0 V
GND = 0 V
Condition 2
Rating
4.0
−0.5
to V
CC
1.89
$40
34
40
$1.5
−40
to +85
−65
to +150
31
27
12
265
Unit
V
V
V
mA
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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3
NB7L1008M
Table 4. DC CHARACTERISTICS
−
CML OUTPUT
V
CC
= 2.375 V to 3.6 V; GND = 0V TA =
−40°C
to 85°C (Note 6)
Symbol
POWER SUPPLY
V
CC
Power Supply Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
3.0
2.375
3.3
2.5
3.6
2.625
V
Characteristic
Min
Typ
Max
Unit
POWER SUPPLY CURRENT
I
CC
V
OH
Power Supply Current, Inputs and Outputs Open
265
315
mA
CML OUTPUTS
(Note 5, Figures 10 and 11)
Output HIGH Voltage
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
– 30
3270
2470
V
CC
– 600
2700
1900
V
CC
– 10
3290
2490
V
CC
– 400
2900
2100
V
CC
3300
2500
V
CC
– 350
2950
2150
mV
V
OL
Output LOW Voltage
mV
DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED
(Notes 7 and 8) (Figures 6 and 8)
V
IH
V
IL
V
th
V
ISE
V
REFAC
V
REFAC
Output Reference Voltage @ 100
mA
for Capacitor
−
Coupled
Inputs, Only
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
– 1375
V
CC
– 1325
V
CC
– 1200
V
CC
– 1200
V
CC
– 1100
V
CC
– 1075
mV
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
Input Threshold Reference Voltage Range
Single−Ended Input Voltage (V
IH
– V
IL
)
V
th
+ 100
GND
1100
200
V
CC
V
th
– 100
V
CC
– 100
1200
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (IN, IN)
(Note 9) (Figures 4 and 7)
V
IHD
V
ILD
V
ID
I
IH
I
IL
R
TIN
R
TOUT
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input HIGH Current
Input LOW Current
1100
GND
100
−150
−150
40
5
V
CC
V
IHD
−
100
1200
+150
+150
mV
mV
mV
mA
mA
TERMINATION RESISTORS
Internal Input Termination Resistor
Internal Output Termination Resistor
45
45
50
50
55
55
W
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. CML outputs loaded with 50
W
to V
CC
for proper operation.
6. Input and output parameters vary 1:1 with V
CC
.
7. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
8. V
th
is applied to the complementary input when operating in single−ended mode.
9. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
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NB7L1008M
Table 5. AC CHARACTERISTICS
V
CC
= 2.375 V to 3.6 V; GND = 0V TA =
−40°C
to 85°C (Note 10)
Symbol
f
DATA
f
INCLK
V
OUTPP
Characteristic
Maximum Operating Input Data Rate
Maximum Input Clock Frequency, V
OUTPP
w
200 mV
Output Voltage Amplitude (see Figures 2 and 5, Note 11)
f
in
v
4 GHz
f
in
v
6 GHz
Input Common Mode Range (Differential Configuration,
Note 12, Figure 9)
Propagation Delay to Output Differential, IN/IN to Qn/Qn
Propagation Delay Temperature Coefficient
−40°C
to +85°C
Output Clock Duty Cycle f
in
v
6 GHz
Duty Cycle Skew (Note 13)
Within Device Skew (Note 14)
Device to Device Skew (Note 15)
Clock Jitter RMS, 1000 Cycles (Note 16) f
in
v
6 GHz
Data Dependent Jitter (DDJ) (Note 17)
v10
Gb/s
Input Voltage Swing (Differential Configuration) (Note 18)
(Figure 5)
Output Rise/Fall Times (20%
−
80%) Qn, Qn
100
20
45
45
Min
10
6
200
200
600
100
160
35
49/51
0.15
7
25
0.2
3
55
1
25
70
0.8
20
1200
70
Typ
12
8
400
350
V
CC
−
50
250
Max
Unit
Gb/s
GHz
mV
V
CMR
t
PLH
, t
PHL
t
PLH
TC
t
DC
t
SKEW
mV
ps
fs/°C
%
ps
t
JITTER
V
INPP
t
r
, t
f
ps
mV
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured using a 400 mV source, 50% duty cycle 1 GHz clock source. All outputs must be loaded with external 50
W
to V
CC
. Input
edge rates 40 ps (20%
−
80%).
11. Output voltage swing is a single−ended measurement operating in differential mode.
12. VIHD
MIN
≥
1100 mV.
13. Duty cycle skew is measured between differential outputs using the deviations of the sum of T
pw
−
and T
pw
+ @ 1 GHz.
14. Within device skew compares coincident edges.
15. Device to device skew is measured between outputs under identical transition
16. Additive CLOCK jitter with 50% duty cycle clock signal.
17. Additive Peak−to−Peak jitter with input NRZ data at PRBS23.
18. Input voltage swing is a single−ended measurement operating in differential mode.
500
OUTPUT VOLTAGE AMPLITUDE
(mV)
450
Q Output Amplitude (mV)
400
IN
350
300
250
200
V
T
50
W
IN
50
W
.
V
CC
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
Figure 3. Input Structure
f
out
, CLOCK OUTPUT FREQUENCY (GHz)
Figure 2. Output Voltage Amplitude (V
OUTPP
)
vs. Input Frequency (f
in
) at Ambient
Temperature (Typical)
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