DM54ALS1000AJ datasheet, PDF - EEWORLD Datasheet

DM54ALS1000AJ: DescriptionIC,LOGIC GATE,QUAD 2-INPUT NAND,ALS-TTL,DIP,14PIN,CERAMIC; Categorylogic logic; File Size62KB，2 Pages; ManufacturerNational Semiconductor（TI ）; Websitehttp://www.ti.com

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DM54ALS1000AJ Overview

IC,LOGIC GATE,QUAD 2-INPUT NAND,ALS-TTL,DIP,14PIN,CERAMIC

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
package instruction	DIP, DIP14,.3
Reach Compliance Code	compliant
JESD-30 code	R-XDIP-T14
JESD-609 code	e0
Logic integrated circuit type	NAND GATE
Number of terminals	14
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC
encapsulated code	DIP
Encapsulate equivalent code	DIP14,.3
Package shape	RECTANGULAR
Package form	IN-LINE
power supply	5 V
Certification status	Not Qualified
Schmitt trigger	NO
Nominal supply voltage (Vsup)	5 V
surface mount	NO
technology	TTL
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Base Number Matches	1

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Shortcut: L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

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