LD82C55A-2 datasheet, PDF - EEWORLD Datasheet

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LD82C55A-2: DescriptionParallel I/O Port, 24 I/O, CMOS, CDIP40, DIP-40; CategoryThe embedded processor and controller Microcontrollers and processors; File Size523KB，23 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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LD82C55A-2 Overview

Parallel I/O Port, 24 I/O, CMOS, CDIP40, DIP-40

LD82C55A-2 Parametric

Parameter Name	Attribute value
Parts packaging code	DIP
package instruction	DIP,
Contacts	40
Reach Compliance Code	unknown
ECCN code	EAR99
maximum clock frequency	8 MHz
External data bus width	8
JESD-30 code	R-GDIP-T40
length	52.325 mm
Number of I/O lines	24
Number of ports	3
Number of terminals	40
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	CERAMIC, GLASS-SEALED
encapsulated code	DIP
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
Maximum seat height	5.72 mm
Maximum slew rate	10 mA
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
width	15.24 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches	1

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LD82C55A-2 Related Products

	LD82C55A-2	QD82C55A-2	D82C55A-2	QP82C55A-2	QN82C55A-2	TD82C55A-2
Description	Parallel I/O Port, 24 I/O, CMOS, CDIP40, DIP-40	Parallel I/O Port, 24 I/O, CMOS, CDIP40, DIP-40	Parallel I/O Port, 24 I/O, CMOS, CDIP40, DIP-40	Parallel I/O Port, 24 I/O, CMOS, PDIP40, DIP-40	Parallel I/O Port, 24 I/O, CMOS, PQCC44, PLASTIC, LCC-44	Parallel I/O Port, 24 I/O, CMOS, CDIP40, DIP-40
Parts packaging code	DIP	DIP	DIP	DIP	LCC	DIP
package instruction	DIP,	DIP,	DIP,	DIP, DIP40,.6	QCCJ,	DIP,
Contacts	40	40	40	40	44	40
Reach Compliance Code	unknown	unknown	unknown	compliant	unknown	unknown
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
maximum clock frequency	8 MHz	8 MHz	8 MHz	8 MHz	8 MHz	8 MHz
External data bus width	8	8	8	8	8	8
JESD-30 code	R-GDIP-T40	R-GDIP-T40	R-GDIP-T40	R-PDIP-T40	S-PQCC-J44	R-GDIP-T40
length	52.325 mm	52.325 mm	52.325 mm	52.26 mm	16.6 mm	52.325 mm
Number of I/O lines	24	24	24	24	24	24
Number of ports	3	3	3	3	3	3
Number of terminals	40	40	40	40	44	40
Maximum operating temperature	85 °C	70 °C	70 °C	70 °C	70 °C	85 °C
Package body material	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, GLASS-SEALED
encapsulated code	DIP	DIP	DIP	DIP	QCCJ	DIP
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	SQUARE	RECTANGULAR
Package form	IN-LINE	IN-LINE	IN-LINE	IN-LINE	CHIP CARRIER	IN-LINE
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	5.72 mm	5.72 mm	5.72 mm	5.08 mm	4.57 mm	5.72 mm
Maximum slew rate	10 mA	10 mA	10 mA	10 mA	10 mA	10 mA
Nominal supply voltage	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	NO	NO	NO	YES	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	J BEND	THROUGH-HOLE
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	2.54 mm	1.27 mm	2.54 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	QUAD	DUAL
width	15.24 mm	15.24 mm	15.24 mm	15.24 mm	16.6 mm	15.24 mm
uPs/uCs/peripheral integrated circuit type	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE	PARALLEL IO PORT, GENERAL PURPOSE
Maker	-	Intel	-	Intel	Intel	Intel
Maximum supply voltage	-	5.5 V	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage	-	4.5 V	4.5 V	4.5 V	4.5 V	-

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