November 2006
rev 0.3
3.3V 1:8 LVCMOS PLL Clock Generator
Features
•
•
•
•
•
1:8 PLL based low-voltage clock generator
Supports zero-delay operation
3.3V power supply
Generates clock signals up to 125MHz
PLL guaranteed to lock down to 145MHz, output
frequency = 36.25MHz
•
•
•
•
•
•
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Maximum output skew of 150 pS
Differential LVPECL reference clock input
External PLL feedback
Drives up to 16 clock lines
32 lead LQFP & TQFP Packages
Industrial temperature range
Pin
and
function
compatible
to
the
PCS5I9653A
running at either 4x or 8x of the reference clock frequency.
The PCS5I9653A is guaranteed to lock in a low power PLL
mode in the high frequency range (VCO_SEL = 0) down to
PLL = 145 MHz or Fref = 36.25MHz.
The PCS5I9653A has a differential LVPECL reference
input long with an external feedback input. The device is
ideal for use as a zero delay, low skew fanout buffer. The
device performance has been tuned and optimized for zero
delay performance. The PLL_EN and BYPASS controls
select the PLL bypass configuration for test and diagnosis.
In this configuration, the selected input reference clock is
bypassing the PLL and routed either to the output dividers
or directly to the outputs. The PLL bypass configurations
are
fully
static
and
the
minimum
clock
frequency
specification and all other PLL characteristics do not apply.
The outputs can be disabled (high-impedance) and the
device reset by asserting the MR/OE pin. Asserting MR/OE
also causes the PLL to loose lock due to missing feedback
signal presence at FB_IN. Deasserting MR/OE will enable
the outputs and close the phase locked loop, enabling the
PLL to recover to normal operation. The PCS5I9653A is
fully 3.3V compatible and requires no external loop filter
components. The inputs (except PCLK) accept LVCMOS
except signals while the outputs provide LVCMOS
compatible levels with the capability to drive terminated
50Ω transmission lines. For series terminated transmission
lines, each of the PCS5I9653A outputs can drive one or
two traces giving the devices an effective fanout of 1:16.
The device is packaged in a 7x7 mm2 32-lead LQFP &
TQFP Packages.
MPC953,MPC9653A and MPC9653
Functional Description
The PCS5I9653A utilizes PLL technology to frequency lock
its outputs onto an input reference clock. Normal operation
of the PCS5I9653A requires the connection of the QFB
output to the feedback input to close the PLL feedback path
(external feedback). With the PLL locked, the output
frequency is equal to the reference frequency of the device
and VCO_SEL selects the operating frequency range of 25
to 62.5MHz or 50 to 125MHz. The two available post-PLL
dividers selected by VCO_SEL (divide-by-4 or divide-by-8)
and the reference clock frequency determine the VCO
frequency. Both must be selected to match the VCO
frequency range. The internal VCO of the PCS5I9653A is
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006
rev 0.3
Block Diagram
PCS5I9653A
Figure 1. PCS5I9653A Logic Diagram
Pin Configuration
PCS5I9653A
Figure 2. PCS5I9653A 32-Lead Package Pinout
(Top View)
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
2 of 13
November 2006
rev 0.3
Table 1: Pin Configuration
Pin #
8,9
2
32
31
30
10
26,24,22,20,18,16,14,12
28
7,13,17,21,25,29
1
PCS5I9653A
Pin Name
PCLK,
PCLK
FB_IN
VCO_SEL
BYPASS
PLL_EN
MR/OE
Q0-7
QFB
GND
VCC_PLL
I/O
Input
Input
Input
Input
Input
Input
Output
Output
Supply
Supply
Type
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
VCC
Function
PECL reference clock signal
PLL feedback signal input, connect to QFB
Operating frequency range select
PLL and output divider bypass select
PLL enable/disable
Output enable/disable (high-impedance tristate) and
device reset
Clock outputs
Clock output for PLL feedback, connect to FB_IN
Negative power supply (GND)
PLL positive power supply (analog power supply). It is
recommended to use an external RC filter for the analog
power supply pin VCC_PLL. Please see applications
section for details
Positive power supply for I/O and core. All VCC pins must
be connected to the positive power supply for correct
operation
No Connect
11,15,19,23,27
3,4,5,6
VCC
NC
Supply
-
VCC
-
Table 2: Function Table
Control
PLL_EN
Default
1
0
Test mode with PLL bypassed. The reference
clock (PCLK) is substituted for the internal VCO
output. PCS5I9653A is fully static and no
minimum frequency limit applies. All PLL related
AC characteristics are not applicable.
Test mode with PLL and output dividers
bypassed. The reference clock (PCLK) is directly
routed to the outputs. PCS5I9653A is fully static
and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
VCO ÷ 1 (High frequency range).
fREF =fQ0-7 =4 . fVCO
1
Selects the VCO output
1
BYPASS
1
Selects the output dividers.
VCO_SEL
1
VCO ÷ 2 (Low output range).
fREF =fQ0-7 =8 . fVCO
Outputs disabled (high-impedance state) and
reset of the device. During reset the PLL
feedback loop is open. The VCO is tied to its
lowest frequency. The length of the reset
pulse should be greater than one reference
clock cycle (PCLK).
MR/OE
0
Outputs enabled (active)
Note: 1 PLL operation requires BYPASS=1 and PLL_EN=1.
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
3 of 13
November 2006
rev 0.3
Table 3: General Specifications
Symbol
VTT
MM
HBM
LU
CPD
CIN
PCS5I9653A
Characteristics
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
Power Dissipation Capacitance
Input Capacitance
Min
200
2000
200
Typ
VCC÷2
Max
Unit
V
V
V
mA
Condition
10
4.0
pF
pF
Per output
Inputs
Table 4: Absolute Maximum Ratings
1
Symbol
VCC
VIN
VOUT
IIN
IOUT
TS
Characteristics
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
Min
-0.3
-0.3
-0.3
Max
3.9
VCC+0.3
VCC+0.3
±20
±50
Unit
V
V
V
mA
mA
°C
Condition
-65
125
Table 5: DC CHARACTERISTICS
(VCC = 3.3V ± 5%, TA =-40°C to +85°C)
Symbol
VIH
VIL
VPP
VCMR
VOH
VOL
ZOUT
IIN
ICC_PLL
ICCQ
5
2
Characteristics
Input high voltage
Input low voltage
Peak-to-peak input voltage
Common Mode Range
Output High Voltage
Output Low Voltage
Output impedance
Input Current
4
Maximum PLL Supply Current
Maximum Quiescent Supply Current
(PCLK)
(PCLK)
Min
2.0
300
1.0
2.4
Typ
Max
VCC +0.3
0.8
VCC-0.6
0.55
0.30
Unit
V
V
mV
V
V
VV
Ω
Condition
LVCMOS
LVCMOS
LVPECL
LVPECL
IOH=-24 mA
3
IOL=24mA
IOL=12mA
VIN=VCC or
GND
VCC_PLL Pin
All
VCC Pins
14 -17
±200
10
15
15
µA
mA
mA
Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
2
VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR
range and the input swing lies within the VPP (DC) specification.
3
The PCS3P9653A is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50
Ω
parallel terminated
transmission line to a termination voltage of V
TT
. Alternatively, the device drives up to two 50
Ω
series terminated transmission lines. The
PCS3P9653A meets the VOH and VOL specification of the PCS3P953 (VOH > VCC-0.6V at IOH=-20mA and VOL > 0.6V at IOL=20mA).
4
Inputs have pull-down or pull-up resistors affecting the input current.
5
OE/MR=1 (outputs in high-impedance state).
1
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
4 of 13
November 2006
rev 0.3
Table 6: AC CHARACTERISTICS
(VCC = 3.3V ± 5%, TA = -40°C to +85°C)
6
Symbol
fREF
fVCO
fVCOlock
fMAX
VPP
VCMR
t(Ø)
tPD
tsk(O)
tsk(PP)
DC
tR,tF
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
tJIT(Ø)
BW
tLOCK
13
PCS5I9653A
Characteristics
Input reference frequency
PLL mode, external feedback
÷4 feedback
÷8 feedback
8
7
Min
50
25
9
Typ
Max
125
62.5
200
500
500
125
62.5
1000
VCC-0.75
125
3.3
7.0
150
1.5
55
1.0
7.0
6.0
100
100
25
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
mV
V
nS
pS
nS
nS
pS
nS
%
nS
nS
nS
pS
pS
pS
MHz
Condition
PLL locked
PLL locked
Input reference frequency in PLL bypass mode
VCO operating frequency range
10
,
11
VCO lock frequency range
Output Frequency
Peak-to-peak input voltage
Common Mode Range
Input Reference Pulse Width
14
12
0
200
145
50
25
450
1.2
2
-75
1.2
3.0
÷4 feedback
9
÷8 feedback
PCLK
PCLK
8
PLL locked
PLL locked
LVPECL
LEPVCL
PLL locked
tPW,MIN
Propagation Delay (static phase offset)
15
PCLK to FB_IN
Propagation Delay
PLL and divider bypass (BYPASS=0), PCLK to Q0-7
PLL disable (BYPASS=1 and PLL_EN=0), PCLK to Q0-7
Output-to-output Skew
16
Device-to-device Skew in PLL and divider bypass
17
Output duty cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
18
I/O Phase Jitter
RMS (1
σ)
PLL closed loop bandwidth
19
PLL mode, external feedback
Maximum PLL Lock Time
BYPASS=0
PLL locked
0.55 to 2.4V
45
0.1
50
÷ 4 feedback
8
÷8 feedback
9
0.8-4
0.5 -1.3
10
mS
6
7
AC characteristics apply for parallel output termination of 50Ω to VTT.
÷4 PLL feedback (high frequency range) requires VCO_SEL=0, PLL_EN=1, BYPASS=1 and MR/OE=0.
8
÷8 PLL feedback (low frequency range) requires VCO_SEL=1, PLL_EN=1, BYPASS=1 and MR/OE=0.
9
In bypass mode, the PCS3P9653A divides the input reference clock.
10
The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB.
11
fVCO is frequency range where AC parameters are guaranteed.
12
fVCOlock is frequency range that the PLL guaranteed to lock, AC parameters only guaranteed over fVCO.
13
VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
14
range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(
Ø
).
Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN . fREF . 100% and DCREF,MAX = 100% - DCREF,MIN. E.g. at
fREF=100 MHz the input duty cycle range is 20% < DC < 80%.
Valid for fREF=50 MHz and FB=÷8 (VCO_SEL=1). For other reference frequencies: t(
Ø
) [ps] = 50 ps ± (1÷(120 . fREF)).
See application section for part-to-part skew calculation in PLL zero-delay mode.
17
For a specified temperature and voltage, includes output skew.
18
I/O phase jitter is reference frequency dependent. See application section for details.
19
-3 dB point of PLL transfer characteristics.
15
16
3.3V 1:8 LVCMOS PLL Clock Generator
Notice: The information in this document is subject to change without notice.
5 of 13
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