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PCS5P9774G-52-ET

Description
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
File Size472KB,12 Pages
ManufacturerPulseCore Semiconductor Corporation
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PCS5P9774G-52-ET Overview

2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer

September 2006
rev 0.4
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
Output frequency range: 8.3MHz to 125MHz
Input frequency range: 4.2MHz to 62.5MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150pS max output-output skew
PLL bypass mode
‘SpreadTrak’
Output enable/disable
Pin compatible with MPC9774 and CY29774
Industrial temperature range: -40°C to +85°C
52Pin 1.0mm TQFP package
RoHS Compliance
PCS5I9774
The PCS5I9774 features two reference clock inputs and
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
outputs. Bank A and Bank B divide the VCO output by 4 or
8 while Bank C divides by 8 or 12 per SEL(A:C) settings,
see Functional Table. These dividers allow output to input
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
LVCMOS compatible output can drive 50Ω series or
parallel
terminated
transmission
lines.
For
series
terminated transmission lines, each output can drive one or
two traces giving the device an effective fanout of 1:28.
The PLL is ensured stable given that the VCO is configured
to run between 200MHz to 500MHz. This allows a wide
range of output frequencies from 8.3MHz to 125MHz. For
normal operation, the external feedback input, FB_IN, is
connected to the feedback output, FB_OUT. The internal
VCO is running at multiples of the input reference clock set
by the feedback divider, see Frequency Table.
Functional Description
The
PCS5I9774
is
a
low-voltage
high-performance
125MHz PLL-based zero delay buffer designed for
high-speed clock distribution applications.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully
static and the minimum input clock frequency specification
does not apply.
Block Diagram
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
SELA
÷2/÷4
CLK
STOP
÷2
PLL
200-
500MHZ
÷2/÷4
÷4
CLK
STOP
QA0
QA1
QA2
QA3
QA4
QB0
QB1
QB2
QB3
QB4
SELB
÷4/÷6
SELC
CLK_STP#
CLK
STOP
QC0
QC1
QC2
QC3
FB_OUT
÷4/÷6/÷8/÷12
FB_SEL(1.0)
MR#/OE
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.

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