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86004BGLFT

Description
TSSOP-16, Reel
Categorylogic    logic   
File Size384KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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86004BGLFT Overview

TSSOP-16, Reel

86004BGLFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-16
Contacts16
Manufacturer packaging codePGG16
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresALSO OPERATES AT 3.3V SUPPLY
series86004
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times4
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply2.5/3.3 V
Prop。Delay @ Nom-Sup6.5 ns
propagation delay (tpd)6.5 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.065 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
minfmax31.25 MHz
Base Number Matches1
15.625MHZ TO 62.5MHZ, 1:4 LVCMOS/
LVTTL Zero Delay Clock Buffer
G
ENERAL
D
ESCRIPTION
The 86004 is a high performance 1:4 LVCMOS/LVTTL Clock Buffer.
The 86004 has a fully integrated PLL and can be configured as
zero delay buffer and has an input and output frequency range
of 15.625MHz to 62.5MHz. The VCO operates at a frequency
range of 250MHz to 500MHz. The external feedback allows the
device to achieve “zero delay” between the input clock and the
output clocks. The PLL_SEL pin can be used to bypass the PLL for
system test and debug purposes. In bypass mode, the reference
clock is routed around the PLL and into the internal output divider.
86004
DATASHEET
F
EATURES
• Four LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Single LVCMOS/LVTTL clock input
• CLK accepts the following input levels: LVCMOS or LVTTL
• Output frequency range: 15.625MHz to 62.5MHz
• Input frequency range: 15.625MHz to 62.5MHz
• VCO range: 250MHz to 500MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Fully integrated PLL
• Cycle-to-cycle jitter: 65ps (maximum)
• Output skew: 65ps (maximum)
• Full 3.3V or 2.5V, or 3.3V core/2.5V output operating supply
• 0°C to 70° ambient operating temperature
• Available in lead-free RoHS compliant package
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
86004
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm package body
G Package
Top View
860049 REVISION B 7/10/15
1
©2015 Integrated Device Technology, Inc.
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