PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8741004I
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
G
ENERAL
D
ESCRIPTION
The ICS8741004I is a high performance
Differential-to-LVDS/HCSL Jitter Attenuator
HiPerClockS™
designed for use in PCI Express™ systems. In
some PCI Express systems, such as those found
in desktop PCs, the PCI Express clocks are
generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator
may be required to attenuate high frequency random and
deterministic jitter components from the PLL synthesizer
and from the system board. The ICS8741004I has 3 PLL
bandwidth modes: 200kHz, 400kHz, and 800kHz. The
200kHz mode will provide maximum jitter attenuation, but
with higher PLL tracking skew and spread spectrum
modulation from the motherboard synthesizer may be
attenuated. 400kHz provides an intermediate bandwidth
that can easily track triangular spread profiles, while provid-
ing good jitter attenuation. 800kHz bandwidth provides the
best tracking skew and will pass most spread profiles, but
the jitter attenuation will not be as good as the lower band-
width modes. Because some 2.5Gb serdes have x20
multipliers while others have x25 multipliers, the 8741004I
can be set for 1:1 mode or 5/4 multiplication mode
(i.e. 100MHz input/125MHz output) using the FSEL pins.
F
EATURES
•
Two differential LVDS and two HCSL output pairs
•
One differential clock input
•
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
•
Output frequency range: 98MHz - 160MHz
•
Input frequency range: 98MHz - 128MHz
•
VCO range: 490MHz - 640MHz
•
Cycle-to-cycle jitter: 15ps (typical)
•
3.3V operating supply
•
Three bandwidth modes allow the system designer to
make jitter attenuation/tracking skew design trade-offs
•
-40°C to 85°C ambient operating temperature
•
Available in both standard and lead-free RoHS-compliant
packages
IC
S
PLL B
ANDWIDTH
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~400kHz (Default)
1 = PLL Bandwidth: ~800kHz
The ICS8741004I uses ICS 3
rd
Generation FemtoClock
TM
PLL technology to achive the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package,
making it ideal for use in space constrained applications such
as PCI Express add-in cards.
B
LOCK
D
IAGRAM
OEA PU
F_SELA PD
BW_SEL Float
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
CLK PD
nCLK PU
QA0
F_SELA
0 ÷5
(default)
1 ÷4
P
IN
A
SSIGNMENT
nQA1
QA1
V
DDO
QA0
nQA0
MR
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQB1
QB1
V
DDO
QB0
nQB0
IREF
F_SELB
OEB
GND
GND
nCLK
CLK
nQA0
QA1
Phase
Detector
VCO
490 - 640 MHz
nQA1
QB0
F_SELB
0 ÷5
(default)
1 ÷4
nQB0
QB1
nQB1
M = ÷5 (fixed)
ICS8741004I
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
F_SELB
PD
MR PD
IREF
OEB PU
G Package
Top View
Current Set
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8741004AGI
www.icst.com/products/hiperclocks.html
REV. A MAY 31, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8741004I
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 22
4, 5
6
Name
nQA1, QA1
V
DDO
QA0, nQA0
MR
Power
Output
Input
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs (Qx) to go low and the inver ted outputs
Pulldown
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pullup/
Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
Pulldown
No connect
Analog supply pin.
Frequency select pin for QAx/nQAx outputs.
Pulldown
LVCMOS/LVTTL interface levels.
Core supply pin.
Output enable pin for QA pins. When HIGH, the QAx/nQAx outputs are
active. When LOW, the QAx/nQAx outputs are in a high impedance
Pullup
state. LVCMOS/LVTTL interface levels.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Power supply ground.
Output enable pin for QB pins. When HIGH, the QBx/nQBx outputs are
Pullup
active. When LOW, the QBx/nQBx outputs are in a high impedance
state. LVCMOS/LVTTL interface levels.
Frequency select pin for QBx/nQBx outputs.
Pulldown
LVCMOS/LVTTL interface levels.
A fixed precision resistor (RREF = 475
Ω
) from this pin to ground
provides a reference current used for differential current-mode
QB0/nQB0 clock outputs.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
7
8
9
10
11
12
13
14
15, 16
17
18
19
20, 21
23, 24
BW_SEL
nc
V
DDA
F_SELA
V
DD
OEA
CLK
nCLK
GND
OEB
F_SELB
IREF
nQB0, QB0
QB1, nQB1
Input
Unused
Power
Input
Power
Input
Input
Input
Power
Input
Input
Input
Output
Output
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
T
ABLE
3A. O
UTPUT
E
NABLE
F
UNCTION
T
ABLE
Inputs
OEA
0
1
OEB
0
1
HiZ
Enabled
Outputs
QAx/nQAx
QBx/nQBx
Hi Z
Enabled
T
ABLE
3B. PLL B
ANDWIDTH
/PLL B
YPASS
C
ONTROL
Inputs
PLL_BW
0
1
Float
PLL
Bandwidth
~200kHz
~800kHz
~400kHz
REV. A MAY 31, 2006
8741004AGI
www.icst.com/products/hiperclocks.html
2
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS8741004I
PCI E
XPRESS
™
J
ITTER
A
TTENUATOR
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DDO
+ 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
Typical
3.3
3.3
3.3
25
8
65
Maximum
3.465
3.465
3.465
Units
V
V
V
mA
mA
mA
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol Parameter
V
IH
Input High Voltage
F_SELA, FESL_B,
MR, OEA, OEB
BW_SEL
V
IL
Input Low Voltage
F_SELA, FESL_B,
MR, OEA, OEB
BW_SEL
I
IH
Input High Current
OEA, OEB
BW_SEL, MR,
F_SELA, FESL_B
BW_SEL,
OEA, OEB,
MR, F_SELA,
FESL_B
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
-150
-5
Test Conditions
Minimum Typical
2
V
DD
- 0.3
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
+0.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
I
IL
Input Low Current
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= -40°C
TO
85°C
Symbol
I
IH
I
IL
V
PP
Parameter
Input High Current
Input Low Current
CLK
nCLK
CLK
nCLK
Test Conditions
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
-150
0.15
1.3
V
DD
- 0.85
5
150
Minimum
Typical
Maximum
150
Units
µA
µA
µA
µA
V
V
Peak-to-Peak Input Voltage
V
CMR
Common Mode Input Voltage; NOTE 1, 2
GND + 0.5
NOTE 1: Common mode voltage is defined as V
IH
.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is V
DD
+ 0.3V.
8741004AGI
www.icst.com/products/hiperclocks.html
3
REV. A MAY 31, 2006
Electronics Design Contest
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