EMK33G2J-12.272M TR
Series
RoHS Compliant (Pb-free) 4 Pad 2.5mm x 3.2mm SMD
3.3Vdc LVCMOS MEMS Oscillator
Frequency Tolerance/Stability
±100ppm Maximum over -40°C to +85°C
Duty Cycle
50 ±5(%)
RoHS
Pb
Packaging Options
Tape & Reel
EMK33 G 2 J -12.272M TR
Nominal Frequency
12.272MHz
Output Control Function
Power Down (Disabled Output: Logic Low)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
12.272MHz
±100ppm Maximum over -40°C to +85°C (Inclusive of all conditions: Calibration Tolerance at 25°C,
Frequency Stability over the Operating Temperature Range, Supply Voltage Change, Output Load Change,
First Year Aging at 25°C, 260°C Reflow, Shock, and Vibration)
±1ppm Maximum First Year
-40°C to +85°C
3.3Vdc ±10%
20mA Maximum
90% of Vdd Minimum (IOH=-8mA)
10% of Vdd Maximum (IOL=+8mA)
2nSec Maximum (Measured from 20% to 80% of waveform)
50 ±5(%) (Measured at 50% of waveform)
15pF Maximum
CMOS
Power Down (Disabled Output: Logic Low)
+0.7Vdd Minimum or No Connect to Enable Output, +0.3Vdd Maximum to Disable Output
50µA Maximum (Disabled Output: Logic Low)
500pSec Maximum, 200pSec Typical
50mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Output Control Function
Output Control Input Voltage
Standby Current
Peak to Peak Jitter (tPK)
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Flammability
Mechanical Shock
Moisture Resistance
Moisture Sensitivity Level
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Thermal Shock
Vibration
MIL-STD-883, Method 3015, Class 2, HBM 2000V
UL94-V0
MIL-STD-883, Method 2002, Condition G, 30,000G
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003 (Pads on Bottom of Package Only)
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 1011, Condition B
MIL-STD-883, Method 2007, Condition A, 20G
www.ecliptek.com | Specification Subject to Change Without Notice | Rev K 8/14/2010 | Page 1 of 6
EMK33G2J-12.272M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
POWER DOWN INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% of Waveform
50% of Waveform
20% of Waveform
V
OL
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
OUTPUT DISABLE
(LOGIC LOW)
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State or
Power Down
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev K 8/14/2010 | Page 3 of 6
EMK33G2J-12.272M TR
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
High Temperature Infrared/Convection
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
3°C/second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev K 8/14/2010 | Page 5 of 6
FPGA/CPLD
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