IDT72201L25LB datasheet, PDF - EEWORLD Datasheet

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IDT72201L25LB: DescriptionFIFO, 256X9, 15ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32; Categorystorage storage; File Size196KB，19 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72201L25LB Overview

FIFO, 256X9, 15ns, Synchronous, CMOS, CQCC32, CERAMIC, LCC-32

IDT72201L25LB Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFJ
package instruction	CERAMIC, LCC-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	15 ns
Maximum clock frequency (fCLK)	40 MHz
period time	25 ns
JESD-30 code	R-CQCC-N32
JESD-609 code	e0
length	13.97 mm
memory density	2304 bit
Memory IC Type	OTHER FIFO
memory width	9
Number of functions	1
Number of terminals	32
word count	256 words
character code	256
Operating mode	SYNCHRONOUS
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
organize	256X9
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Encapsulate equivalent code	LCC32,.45X.55
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Filter level	MIL-STD-883 Class B
Maximum seat height	3.048 mm
Maximum standby current	0.1 A
Maximum slew rate	0.1 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	11.43 mm

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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9

CMOS SyncFIFO™

64 X 9, 256 x 9, 512 x 9,

1024 X 9, 2048 X 9 and 4096 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc.

IDT72421

IDT72201

IDT72211

IDT72221

IDT72231

IDT72241

FEATURES:

•

64 x 9-bit organization (IDT72421)

256 x 9-bit organization (IDT72201)

512 x 9-bit organization (IDT72211)

1024 x 9-bit organization (IDT72221)

2048 x 9-bit organization (IDT72231)

4096 x 9-bit organization (IDT72241)

12 ns read/write cycle time (IDT72421/72201/72211)

15 ns read/write cycle time (IDT72221/72231/72241)

Read and write clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can

be set to any depth

Programmable Almost-Empty and Almost-Full flags

default to Empty+7, and Full-7, respectively

Output enable puts output data bus in high-impedance

state

Advanced submicron CMOS technology

Available in 32-pin plastic leaded chip carrier (PLCC),

ceramic leadless chip carrier (LCC), and 32-pin Thin

Quad Flat Pack (TQFP)

For Through-Hole product please see the IDT72420/

72200/72210/72220/72230/72240 data sheet

Military product compliant to MIL-STD-883, Class B

DESCRIPTION:

The IDT72421/72201/72211/72221/72231/72241

SyncFIFO™ are very high-speed, low-power First-In, First-

Out (FIFO) memories with clocked read and write controls.

The IDT72421/72201/72211/72221/72231/72241 have a 64,

256, 512, 1024, 2048, and 4096 x 9-bit memory array,

respectively. These FIFOs are applicable for a wide variety of

data buffering needs such as graphics, local area networks

and interprocessor communication.

These FIFOs have 9-bit input and output ports. The input

port is controlled by a free-running clock (WCLK), and two

write enable pins (

WEN1

, WEN2). Data is written into the

Synchronous FIFO on every rising clock edge when the write

enable pins are asserted. The output port is controlled by

another clock pin (RCLK) and two read enable pins (

REN1

REN2

). The read clock can be tied to the write clock for single

clock operation or the two clocks can run asynchronous of one

another for dual-clock operation. An output enable pin (

) is

provided on the read port for three-state control of the output.

The Synchronous FIFOs have two fixed flags, Empty (

)

and Full (

). Two programmable flags, Almost-Empty (

PAE

)

and Almost-Full (

PAF

), are provided for improved system

control. The programmable flags default to Empty+7 and Full-

7 for

PAE

and

PAF

, respectively. The programmable flag

offset loading is controlled by a simple state machine and is

initiated by asserting the load pin (

The IDT72421/72201/72211/72221/72231/72241 are

fabricated using IDT’s high-speed submicron CMOS

technology. Military grade product is manufactured in

compliance with the latest revision of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WCLK

- D

WEN1

WEN2

INPUT REGISTER

OFFSET REGISTER

WRITE CONTROL

LOGIC

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1024 x 9,

2048 x 9, 4096 x 9

FLAG

LOGIC

PAE

PAF

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

- Q

2655 drw 01

SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Integrated Device Technology, Inc

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

DECEMBER 1995

DSC-2655/6

5.07

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