a
FEATURES
Synchronous Operation
Full-Scale Frequency Set by External System Clock
8-Lead SOT-23 and 8-Lead microSOIC Packages
3 V or 5 V Operation
Low Power: 3 mW (Typ)
Nominal Input Range: 0 to V
REF
True –150 mV Capability Without Charge Pump
V
REF
Range: 2.5 V to VDD
Internal 2.5 V Reference
1 MHz Max Input Frequency
Selectable High Impedance Buffered Input
Minimal External Components Required
APPLICATIONS
Isolation of High Common-Mode Voltages
Low-Cost Analog-to-Digital Conversion
Battery Monitoring
Automotive Sensing
3 V/5 V Low Power, Synchronous
Voltage-to-Frequency Converter
AD7740*
FUNCTIONAL BLOCK DIAGRAM
REFIN/OUT
VDD
AD7740
2.5V
REFERENCE
VIN
X1
VOLTAGE-TO-
FREQUENCY
MODULATOR
FOUT
CLOCK
GENERATION
BUF
GND
CLKOUT
CLKIN
GENERAL DESCRIPTION
The AD7740 is a low-cost, ultrasmall synchronous Voltage-to-
Frequency Converter (VFC). It works from a single 3.0 V to
3.6 V or 4.75 V to 5.25 V supply consuming 0.9 mA. The AD7740
is available in an 8-lead SOT-23 and also in an 8-lead microSOIC
package. Small package, low cost and ease of use were major
design goals for this product. The part contains an on-chip 2.5 V
bandgap reference but the user may overdrive this using an
external reference. This external reference range includes VDD.
The full-scale output frequency is synchronous with the clock
signal on the CLKIN pin. This clock can be generated with the
addition of an external crystal (or resonator) or supplied from a
CMOS-compatible clock source. The part has a maximum
input frequency of 1 MHz.
For an analog input signal that goes from 0 V to V
REF
, the out-
put frequency goes from 10% to 90% of f
CLKIN.
In buffered mode,
the part provides a very high input impedance and accepts a
range of 0.1 V to VDD – 0.2 V on the VIN pin. There is also
an unbuffered mode of operation that allows VIN to go from
–0.15 V to VDD + 0.15 V. The modes are interchangeable using
the BUF pin.
The AD7740 (Y Grade) is guaranteed over the automotive
temperature range of –40°C to +105°C. The AD7740 (K Grade)
is guaranteed from 0°C to 85°C.
PRODUCT HIGHLIGHTS
1. The AD7740 is a single channel, single-ended VFC. It is
available in 8-lead SOT-23 and 8-lead microSOIC packages,
and is intended for low-cost applications. The AD7740 offers
considerable space saving over alternative solutions.
2. The AD7740 operates from a single 3.0 V to 3.6 V or 4.75 V
to 5.25 V supply and consumes typically 0.9 mA when the
input is unbuffered. It also contains an automatic power-down
function.
3. The AD7740 does not require external resistors and capaci-
tors to set the output frequency. The maximum output
frequency is set by a crystal or a clock. No trimming or cali-
bration is required.
4. The analog input can be taken to 150 mV below GND for
true bipolar operation.
5. The specified voltage reference range on REFIN is from
2.5 V to the supply voltage, VDD.
*Protected
under U.S. Patent # 6,147,528.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P Box 9106, Norwood, MA 02062-9106, U.S.A.
.O.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD7740 SPECIFICATIONS
Parameter
2
(VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = 0 V, REFIN = 2.5 V; CLKIN = 1 MHz; All
specifications T
MIN
to T
MAX
unless otherwise noted.)
Unit
Test Conditions/Comments
K, Y Versions
1
Min
Typ
Max
DC PERFORMANCE
Integral Nonlinearity
CLKIN = 32 kHz
3
CLKIN = 1 MHz
CLKIN = 32 kHz
3
CLKIN = 1 MHz
Offset Error
Gain Error
Offset Error Drift
3
Gain Error Drift
3
Power Supply Rejection Ratio
3
ANALOG INPUT, VIN
Nominal Input Span
0.1
Input Current
REFERENCE VOLTAGE
REFIN
5
Nominal Input Voltage
REFOUT
Output Voltage
Output Impedance
3
Reference Drift
3
Line Rejection
3
Line Rejection
3
Reference Noise (0.1 Hz to 10 Hz)
3
FOUT OUTPUT
Nominal Frequency Span
LOGIC INPUTS (CLKIN, BUF)
CLKIN
Input Frequency
Input High Voltage, V
IH
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Low Voltage, V
IL
Input Current
Pin Capacitance
BUF
Input High Voltage, V
IH
Input High Voltage, V
IH
Input Low Voltage, V
IL
Input Low Voltage, V
IL
Input Current
Pin Capacitance
3
±
7
±
7
±
0.1
±
20
±
4
–55
–65
0 – V
REF
8
5
±
0.012
±
0.012
±
0.018
±
0.018
±
35
±
35
±
0.7
% of Span
4
% of Span
% of Span
% of Span
mV
mV
% of Span
µV/°C
ppm of Span/°C
dB
dB
V
V
µA
nA
Unbuffered Mode, External Clock at CLKIN
Unbuffered Mode, Crystal at CLKIN
Buffered Mode, External Clock at CLKIN
Buffered Mode, Crystal at CLKIN
Unbuffered Mode, VIN = 0 V
Buffered Mode, VIN = 0.1 V
∆VDD
=
±
5% (5 V)
∆VDD
=
±
10% (3.3 V)
±
150 mV Overrange Available
Buffered Mode
Unbuffered Mode, VIN = 5.4 V, REFIN = 5.25 V
Buffered Mode, VIN = 0.1 V, REFIN = 2.5 V
VDD – 0.2
10
100
2.5
2.3
2.5
1
±
50
–75
–60
100
VDD
2.7
V
V
kΩ
ppm/°C
dB
dB
µV
p–p
Hz
See Pin Function Description
∆VDD
=
±
5% (5 V)
∆VDD
=
±
10% (3.3 V)
0.1 f
CLKIN
to 0.9 f
CLKIN
VIN = 0 V to V
REF
. See Figure 2
32
3.5
2.5
1000
0.8
0.4
±
2
10
3
2.4
2.1
kHz
V
V
V
V
µA
pF
V
V
V
V
nA
pF
V
V
V
V
mA
mA
µA
µs
For Specified Performance
VDD = 5 V
±
5%
VDD = 3.3 V
±
10%
VDD = 5 V
±
5%
VDD = 3.3 V
±
10%
VIN = 0 V to V
DD
VDD = 5 V
±
5%
VDD = 3.3 V
±
10%
VDD = 5 V
±
5%
VDD = 3.3 V
±
10%
3
4.0
2.1
0.1
3.0
0.9
1.1
30
30
0.8
0.4
±
100
10
LOGIC OUTPUTS (FOUT, CLKOUT)
3
Output High Voltage, V
OH
Output High Voltage, V
OH
Output Low Voltage, V
OL
POWER REQUIREMENTS
V
DD7
I
DD
(Normal Mode)
8
I
DD
(Normal Mode)
8
I
DD
(Power-Down)
Power-Up Time
3
0.4
5.25
1.25
1.5
100
Output Sourcing 200
µA
6
. VDD = 5 V
±
5%
Output Sourcing 200
µA
6
. VDD = 3.3 V
±
10%
Output Sinking 1.6 mA
6
V
IH
= VDD, V
IL
= GND. Unbuffered Mode
V
IH
= VDD, V
IL
= GND. Buffered Mode
Exiting Power-Down (Ext. Clock at CLKIN)
NOTES
1
Temperature range: K Version, 0°C to +85°C; Y Version, –40°C to +105°C; typical specifications are at 25°C.
2
See Terminology.
3
Guaranteed by design and characterization, not production tested.
4
Span = Max output frequency–Min output frequency.
5
Because this pin is bidirectional, any external reference must be capable of sinking/sourcing 400
µA
in order to overdrive the internal reference.
6
These logic levels apply to CLKOUT only when it is loaded with one CMOS load.
7
Operation at VDD = 2.7 V is also possible with degraded specifications.
8
Outputs unloaded. I
DD
increases by C
L
×
V
OUT
×
f
FOUT
when FOUT is loaded. If using a crystal/resonator as the clock source, I
DD
will vary depending on the crystal/resonator
type (see Clock Generation section).
Specifications subject to change without notice.
–2–
REV. A
AD7740
TIMING CHARACTERISTICS
1, 2, 3
(VDD = 3.0 V to 3.6 V, 4.75 V to 5.25 V, GND = O V, REFIN = 2.5 V)
Parameter
f
CLKIN
t
HIGH
:t
LOW
t
1
t
2
t
3
t
4
Limit at T
MIN
, T
MAX
VDD = 3.0 V to 3.6 V
32
1
40:60
60:40
50
2.3
1.6
t
HIGH
±
20
Limit at T
MIN
, T
MAX
VDD = 4.75 V to 5.25 V
32
1
40:60
60:40
35
1.8
1.4
t
HIGH
±
8
Unit
kHz min
MHz max
min
max
ns typ
ns typ
ns typ
ns typ
Conditions/Comments
Clock Frequency
Clock Mark/Space Ratio
CLKIN Edge to FOUT Edge Delay
FOUT Rise Time
FOUT Fall Time
FOUT Pulsewidth
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
Specifications subject to change without notice.
t
HIGH
CLKIN
t
4
FOUT
t
LOW
t
1
t
2
t
3
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS*
(T
A
= 25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
Logic Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V
FOUT Voltage to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Commercial (K Version) . . . . . . . . . . . . . . . . 0°C to +85°C
Automotive (Y Version) . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
Max) . . . . . . . . . . . . . . . . . . 150°C
SOT-23 Package
Power Dissipation . . . . . . . . . . . . . . . . . . (T
J
Max – T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 240°C/W
Lead Temperature (10 secs) . . . . . . . . . . . . . . . . . . 300°C
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . 220 + 5/0°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
microSOIC Package
Power Dissipation . . . . . . . . . . . . . . . . . (T
J
Max – T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W
θ
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W
Lead Temperature (10 secs) . . . . . . . . . . . . . . . . . . . 300°C
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/0°C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
*Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7740 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD7740
PIN CONFIGURATIONS
8-Lead microSOIC
8-Lead SOT-23
CLKOUT
1
CLKIN
2
8
BUF
BUF
1
FOUT
2
8
CLKOUT
AD7740
7
FOUT
microSOIC
6
VDD
GND
3
TOP VIEW
(Not to Scale)
5
VIN
REFIN/OUT
4
7
CLKIN
SOT-23
6
GND
VDD
3
TOP VIEW
(Not to Scale)
5
REFIN/OUT
VIN
4
AD7740
PIN FUNCTION DESCRIPTIONS
8-LEAD microSOIC PIN NUMBERS*
Pin
No.
1
2
Mnemonic
CLKOUT
CLKIN
Function
The crystal/resonator is tied between this pin and CLKIN. In the case of an external clock driving CLKIN, an
inverted clock signal appears on this pin and can be used to drive other circuitry provided it is buffered first.
The master clock for the device may be in the form of a crystal/resonator tied between this pin and CLKOUT.
An external CMOS-compatible clock may also be applied to this input as the clock for the device. If CLKIN
is inactive low for 1 ms (typ), the AD7740 automatically enters power-down.
Ground reference for all the circuitry on-chip.
Voltage Reference Input. This is the reference input to the core of the VFC and defines the span of the VFC.
If this pin is left unconnected, the internal 2.5 V reference is the default reference. Alternatively, a precision
external reference may be used to overdrive the internal reference. The internal reference has high output
impedance in order to allow it to be overdriven.
The analog input to the VFC. It has a nominal input range from 0 V to V
REF
which corresponds to an output
frequency of 10% f
CLKIN
to 90% f
CLKIN
. It has a
±
150 mV overrange. If buffered, it draws virtually no current
from whatever source is driving it.
Power Supply Input. These parts can be operated at 3.3 V
±
10% or 5 V
±
5%. The supply should be
adequately decoupled with a 10
µF
and a 0.1
µF
capacitor to GND.
Frequency Output. FOUT goes from 10% to 90% of f
CLKIN
, depending on VIN.
Buffered Mode Select Pin. When BUF is tied low, the VIN input is unbuffered and the range on the VIN
pin is –0.15 V to VDD + 0.15 V. When it is tied high, VIN is buffered and the range on the VIN pin
is restricted to 0.1 V to VDD – 0.2 V.
3
4
GND
REFIN/OUT
5
VIN
6
7
8
VDD
FOUT
BUF
*Note
that the SOT-23 and microSOIC packages have different pinouts.
ORDERING GUIDE
Model
AD7740KRM
AD7740YRT
AD7740YRM
Temperature Range
0°C to 85°C
–40°C to +105°C
–40°C to +105°C
Package Description
microSOIC Package
SOT-23 Package
microSOIC Package
Package
Option
RM-8
RT-8
RM-8
Branding
Information
VOK
VOY
VOY
–4–
REV. A
AD7740
TERMINOLOGY
INTEGRAL NONLINEARITY
POWER SUPPLY REJECTION RATIO (PSRR)
For the VFC, Integral Nonlinearity (INL) is a measure of the maxi-
mum deviation from a straight line passing through the actual
endpoints of the VFC transfer function. The error is expressed in
% of the actual frequency span:
Frequency Span
=
FOUT(max) – FOUT(min)
OFFSET ERROR
This indicates how the apparent input voltage of the VFC is
affected by changes in the supply voltage. The input voltage is
kept constant at 2 V, V
REF
is 2.5 V and the VDD supply is varied
10% at 3.3 V and
±5%
at 5 V. The ratio of the apparent change
in input voltage to the change in VDD is measured in dBs.
OUTPUT
FREQUENCY
FOUT
0.9 f
CLKIN
GAIN ERROR
Ideally, the output frequency for 0 V input voltage is 10% of
f
CLKIN
in unbuffered mode. The deviation from this value referred
to the input is the offset error at BUF = 0. In buffered mode the
minimum output frequency (corresponding to 0.10 V minimum
input voltage) is 13.2% of f
CLKIN
at V
REF
= 2.5 V. The deviation
from this value referred to the input is the offset error at BUF = 1.
Offset error is expressed in mV.
GAIN ERROR
IDEAL
WITH OFFSET
ERROR ONLY
WITH OFFSET
ERROR AND
GAIN ERROR
0.1
f
CLKIN
0
OFFSET
ERROR
REFIN
INPUT
VOLTAGE
VIN
This is a measure of the span error of the VFC. The gain is the
scale factor that relates the input VIN to the output FOUT.
The gain error is the deviation in slope of the actual VFC transfer
characteristic from the ideal expressed as a percentage of the full-
scale span. See Figure 2.
OFFSET ERROR DRIFT
Figure 2. Offset and Gain
This is a measure of the change in Offset Error with changes in
temperature. It is expressed in
µV/°C.
GAIN ERROR DRIFT
This is a measure of the change in Gain Error with changes in
temperature. It is expressed in (ppm of span)/°C.
REV. A
–5–
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