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60-000-9109-002

Description
PLL Frequency Synthesizer,
CategoryAnalog mixed-signal IC    The signal circuit   
File Size41KB,2 Pages
ManufacturerSmiths Group
Download Datasheet Parametric View All

60-000-9109-002 Overview

PLL Frequency Synthesizer,

60-000-9109-002 Parametric

Parameter NameAttribute value
MakerSmiths Group
Reach Compliance Codeunknown
Analog Integrated Circuits - Other TypesPLL FREQUENCY SYNTHESIZER
JESD-30 codeR-XXMA-X
Number of functions1
Maximum operating temperature85 °C
Minimum operating temperature-54 °C
Package body materialUNSPECIFIED
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Certification statusNot Qualified
Maximum supply voltage (Vsup)18 V
Minimum supply voltage (Vsup)14 V
surface mountNO
Temperature levelINDUSTRIAL
Terminal formUNSPECIFIED
Terminal locationUNSPECIFIED
82
INDIRECT FREQUENCY SYNTHESIZERS
60-000 Series
Series 60-000 Frequency Synthesizers are designed for
use in general purpose RF signal applications where
quick delivery is required.
ELECTRICAL SPECIFICATIONS
Frequency Range:
Operating Bandwidth:
Output Power:
Frequency Stability:
Input Reference:
Note 1
Frequency –
Power –
SYNTHESIZERS
ENVIRONMENTAL SPECIFICATIONS
0.4 to 4.95 GHz
See Table 1
+ 8 dBm, minimum
Same as Ref. input
10 to 100 MHz
+ 3 to + 9 dBm
(Sine or TTL, 50 ohm)
200 kHz to 50 MHz
See Table II
See Figure 1
2.0:1, typical
- 15 dBc, maximum
See Table II
+ 14 to 18 volts
See Table I
Phase Lock (“0” = lock)
Parallel, TTL
Standard Operating Temperature:
(See Option - 002 for - 54 to + 85 °C.)
0 to + 70 °C
MECHANICAL SPECIFICATIONS
Size:
RF Connectors:
See Outline
SMA or GPO
OPTION
- 002 Extended Operating Temperature:
- 54 to + 85 °C
Step Size:
Switching Speed:
Phase Noise:
Output VSWR:
Harmonics:
Spurious:
Power Supply:
DC Current:
BITE Scheme:
Digital Control:
Typical Phase Noise @ 1.0 GHz
200 kHz Step
-50
10 MHz Step
SSB Level (dBc/Hz)
-70
-90
-110
-130
-150
-170
1
5
10
100
1000
Offset Frequency (kHz)
Figure 1
10000
Note 1: K is a ratio of the input reference signal divided by the selected step size as defined below:
Group A: K = Ref. Signal
Step Size
Group B: K =
1
2
[Ref. Signal/Step Size)
Group C: K =
1
4
[Ref. Signal/Step Size)
K must be an even divisible and be a number over the range of 1 to 1023. The output noise will degrade if K
10.
Specifications are subject to change without notice.
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