3.3V 168 pin Registered SDRAM Modules
64MB, 128MB, 256MB,
512MB & 1GB Densities
•
168 Pin JEDEC Standard, Registered 8 Byte Dual-In-Line SDRAM Module
for PC and Server main memory applications
One bank 8M x 72, 16M x 72, 32M x 72 and 64M x 72 organisation
two bank 32M x 72 & 128M x 72 organisation
Optimized for ECC applications with very low input capacitances
JEDEC standard Synchronous DRAMs (SDRAM)
Performance:
-8
f
CK
t
CK
t
AC
Clock frequency (max.)
Clock cycle time (min.)
Clock access time (min.)
CAS latency = 3
CAS latency = 2
100
10
6
6
-8B
100
10
6
7
Units
MHz
ns
ns
ns
•
•
•
•
•
•
Single +3.3V(± 0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E
2
PROM
Utilizes 64M & 256M SDRAMs in TSOPII-54 packages with registers and PLL.
The two bank module uses stacked TSOP54 packages
4096 refresh cycles every 64 ms
Card Size: 133,35 mm x 38.1mm / 43.18mm x 4,00 / 6.50mm with Gold contact pads
This specification largely follows the JEDEC STANDARD 21-C / Release 8 / Section 4.5.7
specification and as far as applicable - INTEL’s “PC SDRAM Registered DIMM Specification”
Rev.1.0 (Feb.98 and Rev.1.1 (Aug. 98).
•
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•
•
•
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Semiconductor Group
1
11.98
Preliminary Information
HYS72V8200GR
HYS72V16200GR
HYS72V32200GR
HYS72V32220GR
HYS72V64200GR
HYS72V128220GR
Rev. 1.0/1.1
Ordering Information
Type
HYS72V8200GR-8
HYS72V8200GR-8B
HYS72V16200GR-8
HYS72V16200GR-8B
HYS72V32220GR-8
HYS72V32220GR-8B
HYS72V32200GR-8
HYS72V32200GR-8B
HYS72V64200GR-8
HYS72V64200GR-8B
HYS72V128220GR-8
HYS72V128220GR-8B
Speed Code
PC100-222-620R
PC100-323-620R
PC100-222-620R
PC100-323-620R
PC100-222-620R
PC100-323-620R
PC100-222-620R
PC100-323-620R
PC100-222-620R
PC100-323-620R
PC100-222-620R
PC100-323-620R
Descriptions
one bank 64 MB Reg. DIMM
INTEL Rev. 1.0
one bank 128 MB Reg. DIMM
INTEL Rev. 1.0
two bank 256 MB Reg. DIMM
INTEL Rev. 1.1
one bank 256 MB Reg. DIMM
INTEL Rev. 1.0
one bank 512 MB Reg. DIMM
INTEL Rev. 1.0
two bank 1 GByte Reg. DIMM
INTEL Rev. 1.1
SDRAM
Technology
64 MBit
64 MBit
64 MBit
(stacked)
256 MBit
256 MBit
256 MBit
(stacked)
Pin Names
A0-A11,A12
BA0, BA1
DQ0 - DQ63
CB0-CB7
RAS
CAS
WE
CKE0, CKE1
CLK0 - CLK3
Address Inputs
Bank Selects
Data Input/Output
Check Bits (x72 organisation only)
Row Address Strobe
Column Address Strobe
Read / Write Input
Clock Enable
Clock Input
DQMB0 - DQMB7
CS0 - CS3
REGE
VDD
VSS
SCL
SDA
N.C.
Data Mask
Chip Select
Register Enable
Power (+3.3 Volt)
Ground
Clock for Presence Detect
Serial Data Out
No Connection
Address Format:
Density
64 MB
128 MB
256 MB
256 MB
512 MB
1 GB
Org.
8M x 72
16M x 72
32M x 72
32M x 72
64M x 72
64M x 72
Memory
Banks
1
1
2
1
1
2
SDRAMs
8M x 8
16M x 4
16M x 4
32M x 8
64M x 4
64M x 4
# of
SDRAMs
9
18
36
9
18
36
# of row/bank/
column bits
12 / 2 / 9
12 / 2 / 10
12 / 2 / 10
13 / 2 / 10
13 / 2 / 11
13 / 2 / 11
Refresh
4k
4k
4k
8k
8k
8k
Period
64 ms
64 ms
64 ms
64 ms
64 ms
64ms
Interval
15,6
µs
15,6
µs
15,6
µs
7,8
µs
7,8
µs
7,8
µs
Semiconductor Group
2
Preliminary Information
The HYS72Vx2x0GR family are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which
are organised as 8M x 72, 16M x 72, 32M x 72, 64M x 72 & 128M x 72 high speed memory arrays designed with
Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM
and the design incorporates a PLL circuit for the Clock inputs. The 256MB module is available as one bank and
two bank module version. Use of an on-board register reduces capacitive loading on the input signals but are
delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The
DIMMs use a serial presence detects scheme implemented via a serial E
2
PROM using the two pin I
2
C protocol.
The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint.
Rev. 1.0/1.1
HYS72Vx2x0GR
Registered SDRAM-Modules
Pin Configuration
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
Symbol
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
DQ8
VSS
DQ9
DQ10
DQ11
DQ12
DQ13
VCC
DQ14
DQ15
CB0
CB1
VSS
NC
NC
VCC
WE
DQMB0
DQMB1
CS0
DU
VSS
A0
A2
A4
A6
A8
A10 (AP)
BA1
VCC
VCC
CLK0
PIN #
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
VSS
DU
CS2
DQMB2
DQMB3
DU
VCC
NC
NC
CB2
CB3
VSS
DQ16
DQ17
DQ18
DQ19
VCC
DQ20
NC
DU
CKE1
VSS
DQ21
DQ22
DQ23
VSS
DQ24
DQ25
DQ26
DQ27
VCC
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
SDA
SCL
VCC
PIN #
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
VSS
DQ32
DQ33
DQ34
DQ35
VCC
DQ36
DQ37
DQ38
DQ39
DQ40
VSS
DQ41
DQ42
DQ43
DQ44
DQ45
VCC
DQ46
DQ47
CB4
CB5
VSS
NC
NC
VCC
CAS
DQMB4
DQMB5
NC
RAS
VSS
A1
A3
A5
A7
A9
BA0
A11
VCC
CLK1
A12
PIN #
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
VSS
CKE0
CS3
DQMB6
DQMB7
NC
VCC
NC
NC
CB6
CB7
VSS
DQ48
DQ49
DQ50
DQ51
VCC
DQ52
NC
DU
REGE
VSS
DQ53
DQ54
DQ55
VSS
DQ56
DQ57
DQ58
DQ59
VCC
DQ60
DQ61
DQ62
DQ63
VSS
CLK3
NC
SA0
SA1
SA2
VCC
Semiconductor Group
3
Preliminary Information
Rev. 1.0/1.1
HYS72Vx2x0GR
Registered SDRAM-Modules
RCS0
RDQMB0
DQ(7:0)
CS
DQM
DQ0-DQ7
D0
CS
RDQMB1
DQ(15:8)
DQM
DQ0-DQ7
D1
CS WE
DQM
RCB(7:0)
RCS2
RDQMB2
DQ(23:16)
CS
DQM
DQ0-DQ7
D2
CS
RDQMB3
DQ(31:24)
VCC
C
VSS
D0 - D8, Reg., DLL
SA0
SA1
SA2
SCL
Notes:
1.) DQ wiring may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2.) All resistors are 10 Ohm unless otherwise noted
*) A12 is only used for 32M x 72 organisation
CS
RDQMB4
DQ(39:32)
DQM
DQ0-DQ7
D4
CS
RDQMB5
DQ(47:40)
DQM
DQ0-DQ7
D5
DQ0-DQ7
D8
CS
RDQMB6
DQ(55:48)
DQM
DQ0-DQ7
D6
CS
RDQMB7
DQ(63:56)
D3
DQM
DQ0-DQ7
D7
E
2
PROM (256wordx8bit)
SA0
SA1
SA2
SCL
DQM
DQ0-DQ7
D0 - D8, Reg., DLL
SDA
WP
47k
CLK0
20pF
PLL
SDRAMs D0-D8
CS0/CS2
DQMB0-7
BA0,BA1
A0-11,12*)
RAS
CAS
CKE0
WE
Vcc
REGE
10k
RCS0/RCS2
RDQMB0-7
RBA0,RBA1
RA0-11,12
RRAS
RCAS
RCKE0
RWE
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
SDRAMs D0-D8
Register
CLK1,CLK2,CLK3
30pF
Block Diagram for one bank 8M x 72 & 32M x 72 SDRAM DIMM modules
HYS72V8200GR / HYS72V32200GR using x8 organised SDRAMs
Semiconductor Group
4
Preliminary Information
Rev. 1.0/1.1
HYS72Vx2x0GR
Registered SDRAM-Modules
RCS0
RDQMB0
DQM CS
DQ0-DQ3
DQ0-DQ3
DQM CS
DQ4-DQ7
RDQMB1
DQM CS
DQ8-DQ11
DQ0-DQ3
DQM CS
DQ12-DQ15
DQ0-DQ3
DQM CS
CB0-CB3
RCS2
RDQMB2
DQM CS
DQ16-DQ19
DQ0-DQ3
DQM CS
DQ20-DQ23
RDQMB3
DQM CS
DQ24-DQ27
DQ0-DQ3
DQM CS
DQ28-DQ31
CLK0
20pF
RDQMB4
DQ32-DQ35
DQM CS
DQ0-DQ3
DQM CS
D8
D0
DQ0-DQ3
DQ36-DQ39
D1
RDQMB5
DQ0-DQ3
DQM CS
D9
D2
DQ40-DQ43
DQ0-DQ3
DQM CS
D10
D3
DQ44-DQ47
DQ0-DQ3
DQM CS
D11
DQ0-DQ3
D16
CB4-CB7
RDQMB6
DQ48-DQ51
DQ0-DQ3
D17
DQM CS
DQ0-DQ3
DQM CS
D12
D4
DQ52-DQ55
D5
RDQMB7
DQM CS
D6
DQ56-DQ59
DQ0-DQ3
DQ0-DQ3
DQ0-DQ3
D13
D14
DQM CS WE
D7
DQ61-DQ63
DQ0-DQ3
D15
DQ0-DQ3
PLL
SDRAMs D0-D17
CLK1,CLK2,CLK3
RCS0/RCS2
RDQMB0-7
RBA0,RBA1
RA0-RA11
RRAS
RCAS
RCKE0
RWE
30pF
CS0/CS2
DQMB0-7
BA0,BA1
A0-A11,A12*)
RAS
CAS
CKE0
WE
10k
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
E
2
PROM (256wordx8bit)
SA0
SA0
SDA
SA1
SA1
SA2
WP
SA2
SCL
SCL
47k
VCC
C
VSS
D0 - D17, Reg.,DLL
1.) DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2.) All resistors are 10 Ohm unless otherwise noted
*) A12 is only used for 64M x 72 organisation
Register
D0 - D17, Reg. DLL
Vcc
REGE
Block Diagram for one bank 16M x 72 & 64M x 72 SDRAM DIMM modules
HYS72V16200GR / HYS72V64200GR using x4 organised SDRAMs
Semiconductor Group
5
Preliminary Information
Rev. 1.0/1.1
HYS72Vx2x0GR
Registered SDRAM-Modules