CAT24WC256
256K-Bit I
2
C Serial CMOS EEPROM
(CAT24WC256 not recommended for new designs. See CAT24FC256 data sheet.)
H
GEN
FR
ALO
EE
LE
A
D
F
R
E
E
TM
FEATURES
I
1MHz I
2
C bus compatible*
I
1.8 to 6 volt operation
I
Low power CMOS technology
I
64-byte page write buffer
I
Self-timed write cycle with auto-clear
I
Commercial, industrial and automotive
I
Write protect feature
I
100,000 program/erase cycles
I
100 year data retention
I
8-pin DIP or 8-pin SOIC
I
"Green" package options available
– entire array protected when WP at V
IH
temperature ranges
DESCRIPTION
The CAT24WC256 is a 256K-bit Serial CMOS EEPROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The CAT24WC256
PIN CONFIGURATION
DIP Package (P, L)
A0
A1
NC
VSS
1
2
3
4
8
7
6
5
SOIC Package (J, W, K, X)
A0
A1
NC
VSS
1
2
3
4
8
7
6
5
VCC
WP
SCL
i
D
A0, A1
SDA
SCL
WP
V
CC
V
SS
NC
PIN FUNCTIONS
Pin Name
i
t
n
o
c
s
VCC
WP
SCL
SDA
SDA
d
e
u
n
BLOCK DIAGRAM
EXTERNAL LOAD
DOUT
ACK
VCC
VSS
SDA
START/STOP
LOGIC
WP
CONTROL
LOGIC
features a 64-byte page write buffer. The device oper-
ates via the I
2
C bus serial interface and is available in 8-
pin DIP or 8-pin SOIC packages.
a
P
XDEC
512
s
t
r
512
SENSE AMPS
SHIFT REGISTERS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
EEPROM
512X512
Function
Address Inputs
DATA IN STORAGE
Serial Data/Address
Serial Clock
Write Protect
SCL
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
HIGH VOLTAGE/
TIMING CONTROL
+1.8V to +6.0V Power Supply
Ground
No Connect
A0
A1
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I
2
C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1031, Rev. G
CAT24WC256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –2.0V to +V
CC
+ 2.0V
V
CC
with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Reference Test Method
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
100
2000
100
Typ
MIL-STD-883, Test Method 1033 100,000
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB(5)
I
LI
I
LO
V
IL
Parameter
Power Supply Current - Read
Power Supply Current - Write
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
V
OL1
V
OL2
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
C
I/O(3)
C
IN(3)
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1)
i
D
V
IH
Input High Voltage
Output Low Voltage (V
CC
= +3.0V)
Output Low Voltage (V
CC
= +1.8V)
i
t
n
o
c
s
Test Conditions
f
SCL
= 100 KHz
V
CC
=5V
f
SCL
= 100KHz
V
CC
=5V
V
IN
= GND or V
CC
V
CC
=5V
V
IN
= GND to V
CC
d
e
u
n
Min
–1
V
CC
x 0.7
Conditions
V
I/O
= 0V
V
IN
= 0V
Min
a
P
Max
Max
1
3
1
1
1
V
CC
x 0.3
V
CC
+ 0.5
0.4
0.5
Units
Cycles/Byte
Years
Volts
mA
s
t
r
Units
mA
mA
µA
µA
µA
V
V
V
V
Typ
V
OUT
= GND to V
CC
I
OL
= 3.0 mA
I
OL
= 1.5 mA
Typ
Max
8
6
Units
pF
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
(5) Maximum standby current (I
SB
) = 10µA for the Automotive and Extended Automotive temperature range.
Doc. No. 1031, Rev. G
2
CAT24WC256
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
V
CC
=1.8V - 6.0V V
CC
=2.5V - 6.0V V
CC
=3.0V - 5.5V
Min
F
SCL
t
AA
t
BUF(2)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R(2)
t
F(2)
t
SU:STO
t
DH
t
WR
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
0.1
4.7
4.0
4.7
4.0
4.0
0
Max
100
3.5
0.05
1.2
0.6
1.2
0.6
0.6
0
Min
Max
400
0.9
0.05
0.5
Min
Max
1000
0.55
Units
Power-Up Timing
(2)(3)
Symbol
t
PUR
i
D
t
PUW
Note:
(1) AC measurement conditions:
RL (connects to V
CC
): 0.3V
CC
to 0.7 V
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
i
t
n
o
c
s
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
Parameter
Power-Up to Read Operation
Power-Up to Write Operation
SDA and SCL Fall Time
d
e
u
n
100
100
1.0
0.3
300
300
4.7
0.6
100
50
10
10
Min
a
P
0.25
0.6
0.4
0.25
0
100
0.3
100
0.25
50
10
Typ
Max
1
1
s
t
r
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
µs
ns
ms
Units
ms
ms
kHz
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
3
Doc. No. 1031, Rev. G
CAT24WC256
FUNCTIONAL DESCRIPTION
The CAT24WC256 supports the I
2
C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC256
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1: Device Address Inputs
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
Figure 1. Bus Timing
These pins are hardwired or left connected. When
hardwired, up to four CAT24WC256's may be addressed
on a single bus system. When the pins are left uncon-
nected, the default values are zero.
tF
tLOW
tHIGH
SCL
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
i
D
SDA
SCL
i
t
n
o
c
s
tHD:STA
tAA
8TH BIT
BYTE n
ACK
SDA
SCL
START BIT
tSU:STA
tHD:DAT
d
e
u
n
tR
tLOW
tSU:DAT
tDH
tWR
STOP
CONDITION
a
P
tSU:STO
tBUF
s
t
r
START
CONDITION
ADDRESS
STOP BIT
Doc. No. 1031, Rev. G
4
CAT24WC256
I
2
C BUS PROTOCOL
The features of the I
2
C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC256 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
many as four devices on the same bus. These bits must
compare to their hardwired input pins. The last bit of the
slave address specifies whether a Read or Write opera-
tion is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera-
tion is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC256 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC256 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The five most
significant bits of the 8-bit slave address are fixed as
10100(Fig. 5). The CAT24WC256 uses the next two bits
as address bits. The address bits A1 and A0 allow as
Figure 4. Acknowledge Timing
i
D
i
t
n
o
c
s
SCL FROM
MASTER
1
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
d
e
u
n
8
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC256 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24WC256 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24WC256 will continue to transmit
data. If no acknowledge is sent by the Master, the device
a
P
9
s
t
r
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
0
A1
A0
R/W
5
Doc. No. 1031, Rev. G
京公网安备 11010802033920号
EEWORLD
