-5,-5L:Preliminary
MITSUBISHI LSIs
M2V64S20DTP-5,-5L,-6,-6L,-7,-7L
M2V64S30DTP-5,-5L,-6,-6L,-7,-7L
SDRAM (Rev.4.2)
M2V64S40DTP-5,-5L,-6,-6L,-7,-7L
Jun.'01
(4-BANK x 4,194,304-WORD x
(4-BANK x 2,097,152-WORD x
4-BIT)
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
Some of contents are described for general products and are subject to change w ithout notice.
DESCRIPTION
M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit,
M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit,
M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit,
synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge
of CLK. M 2V64S20DTP, M2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up
to 166MHz for -5, 133MHz for -6, 100MHz for -7, and are suitable for main memory or graphic
memory in computer systems.
FEATURES
M2V64S20/30/40DTP
ITEM
tCLK
tRAS
tRCD
tAC
tRC
Icc1
Clock Cycle Time
Active to Precharge Command Period
Row to Column Delay
Access Time from CLK
Active Command Period
Operation Current
(Max.)
(Single Bank)
(Max.)
(Min.)
(Min.)
(Min.)
(Max.) (CL=3)
(Min.)
V64S20D
V64S30D
V64S40D
Icc6
Self Refresh Current
-5
6ns
42ns
15ns
5.4ns
60ns
90mA
90mA
100mA
1mA
-6
7.5ns
45ns
20ns
5.4ns
67.5ns
75mA
75mA
85mA
1mA
-7
10ns
50ns
20ns
6ns
70ns
70mA
70mA
80mA
1mA
- Single 3.3v±0.3V power supply
- Max. Clock frequency -5:166MHz<3-3-3>, -6:133MHz<3-3-3>, -7:100MHz<2-2-2>
- Fully Synchronous operation referenced to clock rising edge
- 4 bank operation controlled by BA0 & BA1 (Bank Address)
- /CAS latency- 2 and 3 (programmable)
- Burst length- 1, 2, 4, 8 and full page (programmable)
- Burst type- sequential and interleave (programmable)
- Byte Control- DQM L and DQMU for M2V64S40DTP
- Random column access
- Auto precharge and All bank precharge controlled by A10
- Auto refresh and Self refresh
- 4096 refresh cycles every 64ms
- LVTTL Interface
- 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch
MITSUBISHI ELECTRIC
1
-5,-5L:Preliminary
MITSUBISHI LSIs
M2V64S20DTP-5,-5L,-6,-6L,-7,-7L
M2V64S30DTP-5,-5L,-6,-6L,-7,-7L
SDRAM (Rev.4.2)
M2V64S40DTP-5,-5L,-6,-6L,-7,-7L
Jun.'01
(4-BANK x 4,194,304-WORD x
(4-BANK x 2,097,152-WORD x
4-BIT)
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PIN CONFIGURATION (TOP VIEW)
M2V64S20DTP
M2V64S30DTP
M2V64S40DTP
PIN CONFIGURATION
(TOP VIEW)
Vdd
NC
VddQ
NC
DQ0
VssQ
NC
NC
VddQ
NC
DQ1
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
NC
DQ1
VssQ
NC
DQ2
VddQ
NC
DQ3
VssQ
NC
Vdd
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
Vdd
DQ0
VddQ
DQ1
DQ2
VssQ
DQ3
DQ4
VddQ
DQ5
DQ6
VssQ
DQ7
Vdd
DQML
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10(AP)
A0
A1
A2
A3
Vdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Vss
DQ15
VssQ
DQ14
DQ13
VddQ
DQ12
DQ11
VssQ
DQ10
DQ9
VddQ
DQ8
Vss
NC
DQMU
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
DQ7
VssQ
NC
DQ6
VddQ
NC
DQ5
VssQ
NC
DQ4
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
Vss
NC
VssQ
NC
DQ3
VddQ
NC
NC
VssQ
NC
DQ2
VddQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
CLK
CKE
/CS
/RAS
/CAS
/WE
DQ0-15
: Master Clock
: Clock Enable
: Chip Select
: Row Address Strobe
: Column Address Strobe
: Write Enable
: Data I/O
DQM
A0-11
BA0,1
Vdd
VddQ
Vss
VssQ
: Output Disable/ Write Mask
: Address Input
: Bank Address
: Power Supply
: Power Supply for Output
: Ground
: Ground for Output
MITSUBISHI ELECTRIC
2
-5,-5L:Preliminary
MITSUBISHI LSIs
M2V64S20DTP-5,-5L,-6,-6L,-7,-7L
M2V64S30DTP-5,-5L,-6,-6L,-7,-7L
SDRAM (Rev.4.2)
M2V64S40DTP-5,-5L,-6,-6L,-7,-7L
Jun.'01
(4-BANK x 4,194,304-WORD x
(4-BANK x 2,097,152-WORD x
4-BIT)
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
DQ0-7
BLOCK DIAGRAM
I/O Buffer
Memory Array
4096 x512 x8
Cell Array
Memory Array
4096 x512 x8
Cell Array
Memory Array
4096 x512 x8
Cell Array
Memory Array
4096 x512 x8
Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
Mode
Register
Control Circuitry
Address Buffer
Clock Buffer
Control Signal Buffer
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
NOTE : This figure shows the M2V64S30DTP.
The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3.
The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15.
Type Designation Code
These rules are only applied to the Sy nchronous DRAM fam ily .
M2 V 64 S 3 0 D TP -7
Access Item
-5 : 6ns (PC166 3-3-3),
-6 : 7.5ns (P C 133 3-3-3),
-7 : 10ns (P C 100 2-2-2)
T P : T S O P (II)
D : 5th gen.
R eserved for Future Use
2 : x4, 3 : x8, 4 : x16
P ackage T ype
P rocess Generation
Function
Organization
Synchronous DRAM
Density
Interface
Mitsubishi DRAM
64 : 64Mbit
V
: LVT T L
MITSUBISHI ELECTRIC
3
-5,-5L:Preliminary
MITSUBISHI LSIs
M2V64S20DTP-5,-5L,-6,-6L,-7,-7L
M2V64S30DTP-5,-5L,-6,-6L,-7,-7L
SDRAM (Rev.4.2)
M2V64S40DTP-5,-5L,-6,-6L,-7,-7L
Jun.'01
(4-BANK x 4,194,304-WORD x
(4-BANK x 2,097,152-WORD x
4-BIT)
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
PIN FUNCTION
CLK
Input
Master Clock:
All other inputs are referenced to the rising edge of CLK.
Clock Enable:
CKE controls internal clock. When CKE is low, internal clock for the
following cycle is ceased. CKE is also used to select auto /
selfrefresh. After self refresh mode is started, CKE becomes
asynchronous input. Self refresh is maintained as long as CKE is low.
Chip Select:
When /CS is high, any command are masked except tCLK,CKE and
DQM.
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specify the Row / Column Address in conjunction with BA0,1.
The Row Address is specified by A0-11. The Column Address is
specified by A0-9 (x4) / A0-8 (x8) / A0-7 (x16).
A10 is also used to indicate precharge option. When A10 is high at a
read / write command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:
BA0,1 specifies one of four banks to which a command is applied.
BA0,1 must be set with ACT, PRE, READ, WRITE commands.
Data In and Data out are referenced to the rising edge of CLK.
Input / Output
CKE
Input
/CS
/RAS, /CAS, /WE
Input
Input
A0-11
Input
BA0,1
Input
DQ0-3(x4),
DQ0-7(x8),
DQ0-15(x16)
DQM(x4,x8),
DQM(U, L)(x16)
Input
Din Mask and Output Disable:
When DQM(U, L) is high in burst write, Din for the current cycle is
masked. When DQM(U, L) is high in burst read, Dout is disabled at
the next but one cycle.
Power Supply for the memory array and peripheral circuitry.
VddQ and VssQ are supplied to the Output Buffers only.
Vdd, Vss
VddQ, VssQ
Power Supply
Power Supply
MITSUBISHI ELECTRIC
4
-5,-5L:Preliminary
MITSUBISHI LSIs
M2V64S20DTP-5,-5L,-6,-6L,-7,-7L
M2V64S30DTP-5,-5L,-6,-6L,-7,-7L
SDRAM (Rev.4.2)
M2V64S40DTP-5,-5L,-6,-6L,-7,-7L
Jun.'01
(4-BANK x 4,194,304-WORD x
(4-BANK x 2,097,152-WORD x
4-BIT)
8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
64M Synchronous DRAM
BASIC FUNCTIONS
The M 2V64S20, 30 and 40DTP provides basic functions, bank (row) activate, burst read and write, bank
(row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and
/WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option,
and precharge option, respectively. To know the detailed definition of commands, please see the command
truth table.
CLK
/CS
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command
Command
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
def ine basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data appears after
/CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-
precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be written
is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write
(auto-precharge,
WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates burst read
/write operation. When A10 =H at this command, all banks are deactivated (precharge all,
PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H]
REFA command starts auto-refresh cycle. Refresh address are generated internally. After this
command, the banks are precharged automatically.
MITSUBISHI ELECTRIC
5
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