Advance Information
AN1812/D
Rev. 1, 12/2001
Common Footprint for the
MPC750, MPC755,
MPC7400, and MPC7410
CPD Applications
This document describes how to design a platform with a common footprint for the MPC750,
MPC755, MPC7400, and MPC7410; that is, it is intended to help design a single board
compatible with all of these devices. Although this document contains relevant information, it
is not intended to be a complete migration guide for moving from G3- to G4-class systems.
As a general note, refer to the appropriate hardware specifications and user’s manual for the
specific device under consideration.
For this document, the following system definition is assumed for the MPC750, MPC755,
MPC7400 and MPC7410:
•
•
•
64-bit data bus mode
No data retry
Bus operates in 60x mode
Note that all the CPUs can run in 60x bus, and the MPC7400 and MPC7410 have the ability
to run in an enhanced mode MPX.
Main Pin Difference
1.1
Main Pin Difference
This section includes Table 1 which lists the main differences between the MPC750, MPC755, MPC7400
and MPC7410 and the configuration pins. The MPX bus column provides information for designers to take
advantage of the MPX bus mode for future board revisions.
Table 1. Main Pin Difference and Configuration Pins
Pin #
B3
B4
B5
K9
K19
Type
I/O
I/O
Output
Output
Output
MPC750
No Connect
No Connect
No Connect
No Connect
No Connect
MPC755
No Connect
No Connect
No Connect
No Connect
No Connect
MPC7400/
MPC7410
60x Bus
SHD[0]
SHD[1]
No Function
No Function
L2A17
MPC7400/
MPC7410
MPX Bus
SHD[0]
SHD[1]
HIT
DRDY
L2A17
Connect to L2 SRAM. A pull-up
to L2VODD should be used if
MPC750/MPC755 1Mbyte
compatibility is required when
using 2Mbytes of SRAM.
Reserved for future expansion
See hardware specification
document. Should put in a pull
up/down pair for each to allow
any configuration.
Comment
Pull-up (in multi CPU system,
connect together)
1
Pull-up (in multi CPU system,
connect together)
1
Pull-up to OVDD
1
W19
A4
A5
A6
A7
F9
F7
F8
K11
K13
L7
C2
C3
K5
D1
H6
Output
Input
Input
Input
Input
Input
Input
Input
Input
No Connect
PLL_CFG[0]
PLL_CFG[1]
PLL_CFG[2]
PLL_CFG[3]
LSSD_MODE
L2_TSTCLK
L1_TSTCLK
No Connect
VOLDET
No Connect
PLL_CFG[0]
PLL_CFG[1]
PLL_CFG[2]
PLL_CFG[3]
LSSD_MODE
L2_TSTCLK
L1_TSTCLK
No Connect
VOLDET
ABB
CI
WT
DBB
DBWO
DRTRY
L2A18
PLL_CFG[0]
PLL_CFG[1]
PLL_CFG[2]
PLL_CFG[3]
LSSD_MODE
L2_TSTCLK
L1_TSTCLK
CHK
L2OVDD[13]
ABB
CI
WT
DBB
DBWO
No Function
L2A18
PLL_CFG[0]
PLL_CFG[1]
PLL_CFG[2]
PLL_CFG[3]
LSSD_MODE
L2_TSTCLK
L1_TSTCLK
CHK
L2OVDD[13]
ABB
CI
WT
DBB
DTI[0]
2
DTI[1]
2
Pull-up to OVDD
Must be connected to L2OVDD
Pull-up to OVDD
1
I/O or
Output
I/O or
Output
I/O or
Output
I/O or
Output
Input
Input
ABB
CI
WT
DBB
DBWO
DRTRY
Connect to HRESET for no
Data retry mode in 60x bus.
2
Common Footprint for the MPC750, MPC755, MPC7400, and MPC7410
MOTOROLA
I/O Voltage Selection
Table 1. Main Pin Difference and Configuration Pins (continued)
Pin #
G1
A3
W1
A19
1
2
Type
Input
Input
MPC750
DBDIS
TLBISYNC
No Connect
No Connect
MPC755
DBDIS
TLBISYNC
BVSEL
L2VSEL
MPC7400/
MPC7410
60x Bus
No Function
EMODE
BVSEL
L2VSEL
MPC7400/
MPC7410
MPX Bus
DTI[2]
2
EMODE
BVSEL
L2VSEL
Comment
Pull-up to OVDD
1
Pull-up to OVDD (64-bit 60x
bus)
See Table 2 and Table 3 for
voltages.
See the individual hardware specifications document for the recommended resistor value.
DTI[0:2] should be pulled low in MPX bus mode to disable re-ordering.
1.2
I/O Voltage Selection
This section lists the four footprint power planes and displays the section matrix for the I/O voltages.
In addition, the footprint should have four power planes:
•
•
•
•
Ground
The CPU core voltage, [VDD]
The I/O voltage for the system bus, [OVDD]
The I/O voltage for the L2 SRAM interface, [L2OVDD]
The I/O voltages [OVDD and L2OVDD] are selectable on all the CPUs except the MPC750,
which supports 3.3V only on both of these interfaces.
Table 2 and Table 3 show the selection matrix for the I/O voltages:
Table 2. I/O Voltage Selection—BVSEL
BVSEL
0
HRESET
1
¬HRESET
Unconnected
(internal pull-up)
MPC750
N/A
N/A
N/A
N/A
N/A
MPC755
N/A
N/A
OVDD (2.5V/3.3V)
N/A
2.5V/3.3V
MPC7400
1.8V
N/A
3.3V
N/A
3.3V
MPC7410 (Rev E)
1.8V
2.5V
3.3V
3.3V
3.3V
MOTOROLA
Common Footprint for the MPC750, MPC755, MPC7400, and MPC7410
3
I/O Voltage Selection
Table 3. I/O Voltage Selection—L2VSEL
L2VSEL
0
HRESET
1
¬HRESET
Unconnected
(internal pull-up)
MPC750
N/A
N/A
N/A
N/A
N/A
MPC755
N/A
N/A
L2VDD (2.5V/3.3V)
N/A
2.5V/3.3V
MPC7400
1.8V
2.5V
3.3V
N/A
3.3V
MPC7410 (Rev E)
1.8V
2.5V
2.5V
N/A
2.5V
Table 4 pertains to the remaining pins, and the comments are valid for the common footprint.
Table 4. Remaining Pins
Pin #
A13
D2
H11
C1
B13
F2
C13
E5
D13
G7
F12
G3
G6
H2
E2
L3
G5
L4
G4
J4
H7
E1
G2
F3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
A[00]
A[01]
A[02]
A[03]
A[04]
A[05]
A[06]
A[07]
A[08]
A[09]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
A[16]
A[17]
A[18]
A[19]
A[20]
A[21]
A[22]
A[23]
MPC750
A[00]
A[01]
A[02]
A[03]
A[04]
A[05]
A[06]
A[07]
A[08]
A[09]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
A[16]
A[17]
A[18]
A[19]
A[20]
A[21]
A[22]
A[23]
MPC755
MPC7400/
MPC7410
60x or MPX Bus
A[00]
A[01]
A[02]
A[03]
A[04]
A[05]
A[06]
A[07]
A[08]
A[09]
A[10]
A[11]
A[12]
A[13]
A[14]
A[15]
A[16]
A[17]
A[18]
A[19]
A[20]
A[21]
A[22]
A[23]
Comment
4
Common Footprint for the MPC750, MPC755, MPC7400, and MPC7410
MOTOROLA
I/O Voltage Selection
Table 4. Remaining Pins (continued)
Pin #
J7
M3
H3
J2
J6
K3
K2
L2
N3
C4
C5
C6
C7
L6
A8
H1
E7
C2
B8
D7
E3
W12
W11
V11
T9
W10
U9
U10
M11
M9
P8
W7
P9
W9
Input
Output
Output
Input
Output
Output
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Input
I/O
I/O
I/O
I/O
I/O
A[24]
A[25]
A[26]
A[27]
A[28]
A[29]
A[30]
A[31]
AACK
AP[0]
AP[1]
AP[2]
AP[3]
ARTRY
AVDD
BG
BR
CI
CKSTP_IN
CKSTP_OUT
CLKOUT
DH[00]
DH[01]
DH[02]
DH[03]
DH[04]
DH[05]
DH[06]
DH[07]
DH[08]
DH[09]
DH[10]
DH[11]
DH[12]
MPC750
A[24]
A[25]
A[26]
A[27]
A[28]
A[29]
A[30]
A[31]
AACK
AP[0]
AP[1]
AP[2]
AP[3]
ARTRY
AVDD
BG
BR
CI
CKSTP_IN
CKSTP_OUT
CLKOUT
DH[00]
DH[01]
DH[02]
DH[03]
DH[04]
DH[05]
DH[06]
DH[07]
DH[08]
DH[09]
DH[10]
DH[11]
DH[12]
MPC755
MPC7400/
MPC7410
60x or MPX Bus
A[24]
A[25]
A[26]
A[27]
A[28]
A[29]
A[30]
A[31]
AACK
AP[0]
AP[1]
AP[2]
AP[3]
ARTRY
AVDD
BG
BR
CI
CKSTP_IN
CKSTP_OUT
CLKOUT
D[00]
D[01]
D[02]
D[03]
D[04]
D[05]
D[06]
D[07]
D[08]
D[09]
D[10]
D[11]
D[12]
Pull up to OVDD
1
Pull up to OVDD
1
Use filter circuit
2
Pull down if no other master.
Pull up to OVDD
1
Pulled up to OVDD if not used to
reduce noise and power.
Comment
MOTOROLA
Common Footprint for the MPC750, MPC755, MPC7400, and MPC7410
5