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MT58L512V18FS-7.5

Description
Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100
Categorystorage    storage   
File Size418KB,27 Pages
ManufacturerCypress Semiconductor
Download Datasheet Parametric View All

MT58L512V18FS-7.5 Overview

Cache SRAM, 512KX18, 7.5ns, CMOS, PQFP100, PLASTIC, TQFP-100

MT58L512V18FS-7.5 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerCypress Semiconductor
Parts packaging codeQFP
package instructionLQFP,
Contacts100
Reach Compliance Codeunknown
ECCN code3A991.B.2.A
Maximum access time7.5 ns
Other featuresFLOW-THROUGH ARCHITECTURE
JESD-30 codeR-PQFP-G100
JESD-609 codee0
length20 mm
memory density9437184 bit
Memory IC TypeCACHE SRAM
memory width18
Humidity sensitivity level3
Number of functions1
Number of terminals100
word count524288 words
character code512000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize512KX18
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Package shapeRECTANGULAR
Package formFLATPACK, LOW PROFILE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width14 mm
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH SYNCBURST SRAM
8Mb SYNCBURST
SRAM
FEATURES
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (V
DD
)
• Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and
address pipelining
• Clock-controlled and registered addresses, data I/Os
and control signals
• Internally self-timed WRITE cycle
• Burst control (interleaved or linear burst)
• Automatic power-down for portable applications
• 100-pin TQFP package
• 165-pin FBGA
• Low capacitive bus loading
• x18, x32, and x36 versions available
MT58L512L18F, MT58L256L32F,
MT58L256L36F; MT58L512V18F,
MT58L256V32F, MT58L256V36F
3.3V V
DD
, 3.3V or 2.5V I/O, Flow-Through
100-Pin TQFP
1
165-Pin FBGA
OPTIONS
• Timing (Access/Cycle/MHz)
7.5ns/8.8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
• Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
• Packages
100-pin TQFP (2-chip enable)
100-pin TQFP (3-chip enable)
165-pin, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
Part Number Example:
MARKING
-7.5
-8.5
-10
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
MT58L512L18F
MT58L256L32F
MT58L256L36F
MT58L512V18F
MT58L256V32F
MT58L256V36F
T
S
F*
None
IT
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
GENERAL DESCRIPTION
The Micron
®
SyncBurst
SRAM family employs high-
speed, low-power CMOS designs that are fabricated us-
ing an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst counter.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, active LOW chip enable (CE#), two additional
chip enables for easy depth expansion (CE2#, CE2), burst
control inputs (ADSC#, ADSP#, ADV#), byte write
MT58L256V36FT-10
8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM
MT58L512L18F_C.p65 – Rev. 2/02
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002, Micron Technology, Inc.
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