1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and
FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
SKALL
t
PW
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Output Rise/Fall Times, 0.8V
∼
2V
0.3
2
ns
Output Disable Time, OE/RST HIGH to LOW
(3)
0
14
ns
Parameter
(1)
Output Skew Between Rising Edges, Q
0
-Q
4
(and Q/
2
if
PE
= LOW)
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
(and Q/
2
if
PE
= HIGH)
(2)
Output Skew, All Outputs
(2, 5)
Pulse Width, 2xQ output, >40MHz
Pulse Width, Q
0
-Q
4
, Q
5,
Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(6)
SYNC to Phase Lock
Output Enable Time, OE/RST LOW to HIGH
(3)
Min.
—
—
—
T
CY
/2
−
0.4
T
CY
/2
−
0.4
Max.
300
300
500
T
CY
/2 + 0.4
T
CY
/2 + 0.4
0.15
0
10
14
Unit
ps
ps
ps
ns
ns
ns
ps
ms
ns
−
0.15
−
500
—
0
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. Skew measured at selected synchronization edge.
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