ZXBM2001
ZXBM2002 ZXBM2003
Absolute maximum ratings
Parameter
Supply Voltage
Input Current
Power Dissipation
Operating Temp.
Storage Temp.
Symbol
V
CCmax
I
CC
PD
T
OPR
T
STG
Limits
-0.6 to 20
200
500
-40 to 85
-55 to 125
Unit
V
mA
mW
C
C
Electrical Characteristics
(at Tamb = 25°C & Vcc = 12V)
Parameter
Supply Voltage
Supply Current
Hall Amp Input Voltage
Hall Amp Common Mode Voltage
Hall Amp Input Offset
Hall Amp Bias Current
PH1, PH2 Output High
PH1, PH2 Output Off Leakage
Current
PH1, PH2 Output Current
Lock/FG Maximum Collector
Voltage
Lock/FG Sink Current
Lock/FG Low Level O/P Voltage
C
LCK
Charge Current
C
LCK
Discharge Current
Lock condition On:Off ratio
C
LCK
High Threshold Voltage
C
LCK
Low Threshold Voltage
C
PWM
Charge Current
C
PWM
Discharge Current
PWM Frequency
C
PWM
High Threshold Voltage
C
PWM
Low Threshold Voltage
SPD Voltage Control Range
SPD Open Circuit Voltage
V
THH
V
THL
I
PWMC
I
PWMD
F
PWM
V
THH
V
THL
V
SPD
1
1.5
3.6
50
V
CM
V
OFS
V
BS
V
OH
I
OFF
I
OL
V
OH
I
OL
V
OL
I
LCKC
I
LCKD
1:7
-1.8
0.3
-2.8
0.28
1:10
2.0
1.0
4.3
62
24
2.0
1.0
2
5.0
75
V
V
A
A
kHz
V
V
V
V
2
3
V
in
= 1.5V
V
in
= 1.5V
C
PWM
=
0.15nF
0.35
V
CC
-2.2
Symbol
V
CC
I
CC
40
0.5
0.5V
CC
±7
-350
V
CC
-1.8
10
80
V
CC
5
0.5
V
CC
-1.5
Min
4.5
2.2
Typ
Max
18
3.25
Unit
V
mA
mV
V
mV
nA
V
A
mA
V
mA
V
A
A
I
OL
= 5mA
V
in
= 1.5V
V
in
= 1.5V
I
OH
= 80mA
No Load
1
diff p-p
Conditions
Notes:
1
Measured with pins H+, H-, CLCK and CPWM = 0V and all other signal pins open circuit.
2
The 1V minimum represents 100% PWM drive and 2V represents 0% PWM drive.
3
This voltage is determined by an internal resistor network of 52.5k from the pin to Gnd and 19.5k
resistors track each other the absolute values are subject to a 20% manufacturing tolerance.
from the pin to a 2V reference. Whilst both
ISSUE 1 - APRIL 2002
2
ZXBM2001
ZXBM2002 ZXBM2003
Pin Functional Descriptions
1. VCC
- Applied voltage
5. GND
- Ground
This is the device supply voltage. For 5V to 12V fans this
can be supplied directly from the Fan Motor supply. For
fans likely to run in excess of the 18V maximum rating
for the device this will be supplied from an external
regulator such as a zener diode.
2. H+
3. H-
- Hall input
- Hall input
This is the device supply ground return pin and will
generally be the most negative supply pin to the fan.
6. LOCK/FG
- Locked Rotor error output /
Frequency Generator (speed) output
On the ZXBM2001 the Lock/FG pin is designed to be a
dual function pin to provide an indication of the Fans
rotational speed together with an indication of when
the Fan has failed rotating for whatever reason (Rotor
Locked condition). The pin is an open collector drive,
that is there is an active pull down with the high level
being provided by an external pull up resistor. Under
correct operating conditions, and with this external
pull-up in place, this pin will provide an output signal
whose frequency will be twice that of the rotational
frequency of the fan. Should the fan itself stop rotating
for any reason, i.e. an obstruction in the fan blade or a
seized bearing, then the device will enter a Rotor
Locked condition. In this condition the Lock/FG pin will
go high (regardless of the state of the Hall sensor)
when the C
LCK
pin reaches the V
THH
threshold and will
remain high until the fan blades start rotating again.
On the ZXBM2002 variant this pin is Lock. During
normal operation the signal will be low and during a
Locked Rotor condition the pin will go high when the
C
LCK
pin reaches the V
THH
threshold.
For the ZXBM2003 variant this pin is FG. This signal is a
buffered and inverted output of the Hall signal and
therefore provides an output signal whose frequency
will be twice that of the rotational frequency of the fan.
7. C
LCK
- Locked Rotor timing capacitor
The rotor position of the Fan Motor is detected by a Hall
sensor whose output is applied to these pins. This
sensor can be either a 4 pin ‘naked’ Hall device or a 3
pin buffered switching type. For a 4 pin device the
differential Hall output signal is connected to the H+
and H- pins. For a 3 pin buffered Hall sensor the Hall
device output is attached to the H+ pin whilst the H- pin
has an external potential divider attached to hold the
pin at half V
CC
. When H+ is high in relation to H- Ph2 is
the active drive.
4. SPD
- Speed control voltage input
This pin provides control over the Fan Motor speed by
varying the Pulse Width Modulated (PWM) drive ratio
at the Ph1 and Ph2 outputs. This control signal can take
the form of either a voltage input of nominal range 2V
to 1V, representing 0% to 100% drive respectively, or
alternatively a thermistor can be attached to this pin to
control the voltage. The pin has an internal potential
divider between Gnd and an internal 2.0V reference
designed to hold the pin at approximately 1.5V. This
will represent a drive of nominally 50%. The addition of
a 100k NTC thermistor to ground, for example, will
provide a drive nominally 70% at 25°C and 100% at
50°C.
If speed control is not required this pin is can be left
open circuit for 50% drive or tied to ground by a 10k
resistor to provide 100% drive.
If required this pin can also be used as an enable pin.
The application of a voltage of 2.0V to V
CC
will to force
the PWM drive fully off, in effect disabling the drive.
When in a Locked Rotor condition as described above
the Ph1 and Ph2 drive outputs go into a safe drive mode
to protect the external drive devices and the motor
windings. This condition consists of driving the motor
for a short period then waiting for a longer period
before trying again. The frequency at which this takes
place is determined by the size of the capacitor applied
to this CLCK pin. For a 12V supply a value of 1.0uF will
typically provide an ‘On’ (drive) period of 0.33s and an
‘Off’ (wait) period of 4.0s, giving an On:Off ratio of 1:12.
ISSUE 1 - APRIL 2002
4
ZXBM2001
ZXBM2002 ZXBM2003
Locked Rotor timing capacitor
(CONT).
The C
LCK
timing periods are determined by the
following equations:
V
THH
×
C
LCK
I
LCKC
T
on
=
(V
THH
−
V
THL
)
×
C
LCK
I
LCKD
9. PH2
10. PH1
- External transistor driver
- External transistor driver
T
lock
=
T
off
=
These are the Phase drive outputs and are open
darlington emitter followers designed to provide up to
80mA of drive to external transistors as shown in the
Application circuits following. The external transistors
in turn drive the fan motor windings.
(V
THH
−
V
THL
)
×
C
LCK
I
LCKC
Lock and FG Timing Waveform:
Where V
THH
and V
THL
are the C
LCK
pin threshold
voltages and I
LCKC
and I
LCKD
are the charge and
discharge currents.
As these threshold voltages are nominally set to
V
THH
=2V and V
THL
=1V the equations can be simplified
as follows:
T
lock
=
2
×
C
LCK
I
LCKC
T
on
=
C
LCK
I
LCKC
T
off
=
C
LCK
I
LCKD
8. C
PWM
- Sets PWM frequency
This pin has an external capacitor attached to set the
PWM frequency for the Phase drive outputs. A
capacitor value of 0.15nF will provide a PWM
frequency of typically 24kHz.
The C
LCK
timing period (T
pwm
) is determined by the
following equation:
(V
THH
−
V
THL
)
×
C
PWM
(V
THH
−
V
THL
)
×
C
PWM
T
pwm
=
+
I
PWMC
I
PWMD
Lock Timing Example:
Using the equation previously described and to be
found under the C
LCK
pin description:
T
lock
=
Where V
THH
and V
THL
are the C
PWM
pin threshold
voltages and I
PWMC
and I
PWMD
are the charge and
discharge currents.
As these threshold voltages are nominally set to
V
THH
=2V and V
THL
=1V the equations can be simplified
as follows:
C
PWM
C
PWM
+
I
PWMC
I
PWMD
2
×
C
LCK
I
LCKC
T
on
=
C
LCK
I
LCKC
T
off
=
C
LCK
I
LCKD
Using a value of C
LCK
= 1.0uF together with the values
of I
LCKC
and I
LCKD
to be found in the Electrical
Characteristics we can derive the following timings for
operation at 12V and 25°C.
2
×
1.0 F
=
0.714s
2.8 A
T
on
=
1.0 F
=
3.6
s
0.28 A
T
lock
=
T
pwm
=
T
off
=
2
×
1.0 F
=
0.36
s
2.8 A
ISSUE 1 - APRIL 2002
5
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