HYMD512646A8J-D4 datasheet, PDF

Datasheet> All Categories > storage> storage> HYMD512646A8J-D4

HYMD512646A8J-D4: DescriptionUnbuffered DDR SDRAM DIMM; Categorystorage storage; File Size263KB，16 Pages; ManufacturerSK Hynix; Websitehttp://www.hynix.com/eng/

Download Datasheet Parametric Compare View All

HYMD512646A8J-D4 Overview

Unbuffered DDR SDRAM DIMM

HYMD512646A8J-D4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	SK Hynix
Parts packaging code	DIMM
package instruction	DIMM, DIMM184
Contacts	184
Reach Compliance Code	unknow
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz
I/O type	COMMON
JESD-30 code	R-XDMA-N184
length	133.35 mm
memory density	8589934592 bi
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	184
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	128MX64
Output characteristics	3-STATE
Package body material	UNSPECIFIED
encapsulated code	DIMM
Encapsulate equivalent code	DIMM184
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	2.5 V
Certification status	Not Qualified
refresh cycle	8192
Maximum seat height	4 mm
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.5 V
Nominal supply voltage (Vsup)	2.6 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	31.75 mm

Preview

Download Datasheet

View All

128Mx64 bits

Unbuffered DDR SDRAM DIMM

HYMD512646A(L)8-M/K/H/L

DESCRIPTION

Preliminary

Hynix HYMD512646A(L)8-M/K/H/L series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line

Memory Modules (DIMMs) which are organized as 128Mx64 high-speed memory arrays. Hynix HYMD512646A(L)8-

M/K/H/L series consists of sixteen 64Mx8 DDR SDRAM in 400mil TSOPII packages on a 184pin glass-epoxy sub-

strate. Hynix HYMD512646A(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor

of industry standard. It is suitable for easy interchange and addition.

Hynix HYMD512646A(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous

operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs

are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-

ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.

All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD512646A(L)8-M/K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

1GB (128M x 64) Unbuffered DDR DIMM based on

64Mx8 DDR SDRAM

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

100MHz/133MHz

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

•

Data inputs on DQS centers when write (centered

DQ)

Data strobes synchronized with output data for read

and input data for write

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

•

ORDERING INFORMATION

Part No.

HYMD512646A(L)8-M

HYMD512646A(L)8-K

HYMD512646A(L)8-H

HYMD512646A(L)8-L

=2.5V

DDQ

=2.5V

Power Supply

Clock Frequency

133MHz (DDR266 2-2-2)

133MHz (DDR266A)

133MHz (DDR266B)

100MHz (DDR200)

Interface

Form Factor

SSTL_2

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / May. 2003

HYMD512646A8J-D4 Related Products

	HYMD512646A8J-D4	HYMD512646A8-H	HYMD512646A8-L	HYMD512646A8J-D43	HYMD512646A8J-J	HYMD512646AL8-M	HYMD512646AL8J-D4
Description	Unbuffered DDR SDRAM DIMM	Unbuffered DDR SDRAM DIMM	Unbuffered DDR SDRAM DIMM	Unbuffered DDR SDRAM DIMM	Unbuffered DDR SDRAM DIMM	Unbuffered DDR SDRAM DIMM	Unbuffered DDR SDRAM DIMM
Is it Rohs certified?	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Maker	SK Hynix	SK Hynix	SK Hynix	SK Hynix	SK Hynix	SK Hynix	SK Hynix
Parts packaging code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
package instruction	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184	DIMM, DIMM184
Contacts	184	184	184	184	184	184	184
Reach Compliance Code	unknow	unknow	unknow	unknow	unknow	compli	compli
ECCN code	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	DUAL BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	0.7 ns	0.75 ns	0.8 ns	0.7 ns	0.7 ns	0.75 ns	0.7 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
Maximum clock frequency (fCLK)	200 MHz	133 MHz	125 MHz	200 MHz	166 MHz	133 MHz	200 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184	R-XDMA-N184
memory density	8589934592 bi	8589934592 bi	8589934592 bi	8589934592 bi	8589934592 bi	8589934592 bi	8589934592 bi
Memory IC Type	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE	DDR DRAM MODULE
memory width	64	64	64	64	64	64	64
Number of functions	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1
Number of terminals	184	184	184	184	184	184	184
word count	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words	134217728 words
character code	128000000	128000000	128000000	128000000	128000000	128000000	128000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
organize	128MX64	128MX64	128MX64	128MX64	128MX64	128MX64	128MX64
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
encapsulated code	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
Encapsulate equivalent code	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184	DIMM184
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
power supply	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V	2.5 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
refresh cycle	8192	8192	8192	8192	8192	8192	8192
self refresh	YES	YES	YES	YES	YES	YES	YES
Maximum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V	2.7 V
Minimum supply voltage (Vsup)	2.5 V	2.3 V	2.3 V	2.5 V	2.3 V	2.3 V	2.5 V
Nominal supply voltage (Vsup)	2.6 V	2.5 V	2.5 V	2.6 V	2.5 V	2.5 V	2.6 V
surface mount	NO	NO	NO	NO	NO	NO	NO
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
Terminal pitch	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm	1.27 mm
Terminal location	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
length	133.35 mm	-	-	133.35 mm	133.35 mm	-	133.35 mm
Maximum seat height	4 mm	-	-	4 mm	4 mm	-	4 mm
width	31.75 mm	-	-	31.75 mm	31.75 mm	-	31.75 mm

Recommended Resources

Common anode 8-segment digital tube display circuit diagram

This application circuit of LM135-235-335c

Typical integrating circuit diagram for detecting angular displacement

Uncooled detection amplifier circuit

Video amplifier circuit: video amplifier board-6

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components